STRUCTURE AND METHOD FOR MANUFACTURING MOSFET WITH SUPER-STEEP RETROGRADED ISLAND

• US 20070252203A1
• Filed: 07/06/2007
• Published: 11/01/2007
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Leobandung, Effendi, Zhu, Huilong, Mocuta, Dan, Mocuta, Anda
• Granted Patent: US 7,723,750 B2
• Time in Patent Office: Days
• US Class Current: 257/345
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffisivity layer may be Si_1-x-yGe_xZ_y, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

Claims

1. A semiconducting device comprising:

a gate region positioned on a channel portion of a substrate;

said channel portion of said substrate positioned atop a first conductivity type retrograded dopant island and between a set of second conductivity type doped regions; and

the first conductivity type retrograded dopant island substantially aligned to sidewalls of said gate region and having a first doping concentration sufficient to substantially reduce short-channel effects without increasing device leakage.

2. The semiconducting device of claim 1 wherein said channel portion of said substrate comprises a thickness ranging from about 10 nm to about 20 nm and a channel length of approximately 10 nm or less.

3. The semiconducting device of claim 1 wherein said first conductivity retrograded dopant island comprises Si_1-x-yGe_xZ_y, wherein Z comprises a diffusion limiting dopant.

4. The semiconducting device of claim 3 wherein a first conductivity dopant of said first conductivity retrograded dopant island is an n-type dopant and Z is selected from the group consisting of xenon, carbon, germanium, krypton, argon, nitrogen, and combinations thereof.

5. The semiconducting device of claim 3 wherein said first conductivity dopant of said first conductivity retrograded dopant island is a p-type dopant and Z may be selected from the group consisting of xenon, carbon, germanium, krypton, argon, nitrogen, or combinations thereof.

6. The semiconducting device of claim 1 wherein said first conductivity retrograded dopant island has a doping concentration at least an order of magnitude greater than said channel portion.

7. The semiconducting device of claim 1 wherein said set of second conductivity type doped regions comprise SiGe and said channel portion further comprises an internal compressive stress.

8. The semiconducting device of claim 1 wherein said set of second conductivity type doped regions comprise Si:

C and said channel portion further comprises an internal tensile stress.

9. The semiconducting device of claim 1 further comprising deep source/drain regions underlying said second conductivity type doped regions, wherein said deep source/drain regions are separated from said first conductivity type retrograded dopant island by a leakage inhibiting dopant region.

10. An integrated circuit comprising:

at least one semiconducting device comprising a gate region positioned on a channel portion of a substrate, said channel portion of said substrate positioned atop a first conductivity type retrograded dopant island and between a set of second conductivity type doped extension regions, said first conductivity type retrograded dopant island being substantially aligned to said gate region and having a doping concentration that substantially reduces short-channel effects within said at least one semiconducting device without increasing device leakage; and

electrical contact to said at least one semiconducting device.