Semiconductor device and manufacturing method for semiconductor device

• US 20070252211A1
• Filed: 04/25/2007
• Published: 11/01/2007
• Est. Priority Date: 04/26/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yagishita, Atsushi
• Granted Patent: US 7,755,104 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second <110> crystal orientation perpendicular to the current flow direction, and a gate insulating film that is disposed between the semiconductor layer and the gate electrode, wherein a uniaxial tensile strain is applied to the semiconductor layer in the direction of the second <110> crystal orientation perpendicular to the current flow direction.

Claims

1. A semiconductor device that has a pMOS double-gate structure, comprising:

a substrate, the crystal orientation of the top surface of which is (100),

a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <

110>

crystal orientation, and channels are located at sidewall of the semiconductor layer,

a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first <

110>

crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer;

a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first <

110>

crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer;

a gate electrode that is formed on the semiconductor layer in a direction of a second <

110>

crystal orientation perpendicular to the current flow direction,

and a gate insulating film that is disposed between the semiconductor layer and the gate electrode,

wherein a uniaxial tensile strain is applied to the semiconductor layer in the direction of the second <

110>

crystal orientation perpendicular to the current flow direction.

2. The semiconductor device according to claim 1, wherein the gate electrode contains a shrinkable material and the shrinkability causes the uniaxial tensile strain applied to the side wall of the semiconductor layer in the direction of the second <

110>

crystal orientation perpendicular to the current flow direction.

3. The semiconductor device according to claim 2, wherein the shrinkable material is any of TiSi₂, CoSi₂, TiN, W and WSi.

4. The semiconductor device according to claim 1, wherein the substrate is an SOI substrate in the case where the semiconductor layer is made of silicon or a GOI substrate in the case of the semiconductor layer is made of germanium.

5. The semiconductor device according to claim 2, wherein the substrate is an SOI substrate in the case where the semiconductor layer is made of silicon or a GOI substrate in the case of the semiconductor layer is made of germanium.

6. The semiconductor device according to claim 3, wherein the substrate is an SOI substrate in the case where the semiconductor layer is made of silicon or a GOI substrate in the case of the semiconductor layer is made of germanium.

7. A method of manufacturing a semiconductor device having a pMOS double-gate structure, comprising:

forming an insulating film on silicon or germanium layer formed on a substrate, the crystal orientation of the top surface of which is (100),

selectively etching silicon or germanium to form a fin that extends in a direction of a first <

110>

crystal orientation,

forming a gate insulating film on a side wall of the fin,

forming a polysilicon layer that that extends in a direction of a second <

110>

crystal orientation perpendicular to the direction of the first <

110>

crystal orientation on a part of the insulating film on channel region,

removing the insulating film exposed on the fin, selectively siliciding a part of the fin from which the insulating film is removed, thereby forming, in the fin, a source layer and a drain layer that form Schottky junctions with the semiconductor layer; and

selectively siliciding the polysilicon layer to form a gate electrode made of a shrinkable material.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the shrinkable material is any of TiSi₂, and CoSi₂.

9. The method of manufacturing a semiconductor device according to claim 7, wherein the substrate is an SOI substrate in the case where the semiconductor layer is made of silicon or a GOI substrate in the case of the semiconductor layer is made of germanium.

10. The method of manufacturing a semiconductor device according to claim 8, wherein the substrate is an SOI substrate in the case where the semiconductor layer is made of silicon or a GOI substrate in the case of the semiconductor layer is made of germanium.

11. A method of manufacturing a semiconductor device having a pMOS double-gate structure, comprising:

forming an insulating film on silicon or germanium formed on a substrate, the crystal orientation of the top surface of which is (100),

selectively etching silicon or germanium to form a fin that extends in a direction of a first <

110>

crystal orientation,

forming a gate insulating film on a side wall of the fin,

forming a polysilicon layer that extends in a direction of a second <

110>

crystal orientation perpendicular to the direction of the first <

110>

crystal orientation on a part of the insulating film on channel region,

forming insulating gate side walls on side walls of the polysilicon layer,

removing the insulating film exposed on the fin,

selectively siliciding a part of the fin where the insulating film is removed, thereby forming, in the fin, a source layer and a drain layer, Schottky junctions is formed between source/drain and the semiconductor layer,

depositing an interlayer insulating film and etching back the interlayer insulating film to expose the top surface of the polysilicon layer,

selectively removing the polysilicon layer,

and filling a shrinkable material into a gate groove defined by the gate side walls to form a gate electrode.

12. The method of manufacturing a semiconductor device according to claim 11, wherein the shrinkable material is any of TiN, W and WSi.

13. The method of manufacturing a semiconductor device according to claim 11, wherein the substrate is an SOI substrate in the case where the semiconductor layer is made of silicon or a GOI substrate in the case of the semiconductor layer is made of germanium.

14. The method of manufacturing a semiconductor device according to claim 12, wherein the substrate is an SOI substrate in the case where the semiconductor layer is made of silicon or a GOI substrate in the case of the semiconductor layer is made of germanium.