Integrated Chemical Microreactor With Large Area Channels and Manufacturing Process Thereof

• US 20070252224A1
• Filed: 05/01/2007
• Published: 11/01/2007
• Est. Priority Date: 02/29/2000
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Villa, Flavio, Barlocchi, Gabriele, Mastromatteo, Ubaldo
• Granted Patent: US 7,732,192 B2
• Time in Patent Office: Days
• US Class Current: 257/414
• CPC Class Codes: B01J 19/0093 Microreactors, e.g. miniaturised or microfabricated reactors laboratory containers with capillary fluid transport in microfabricated channels or chambers B01L3/5027
• CPC Class Codes: B01J 2219/00783 Laminate assemblies, i.e. the reactor comprising a stack of plates
• CPC Class Codes: B01J 2219/00828 Silicon wafers or plates
• CPC Class Codes: Y10T 436/114998 with treatment or replacement of aspirator element [e.g., cleaning, etc.]

Abstract

The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.

Claims

1. An integrated microreactor comprising:

a) a body of semiconductor material;

b) a channel in said body and having walls and a coating layer of insulating material coating said walls;

c) a diaphragm upwardly closing said channel, said diaphragm comprising a semiconductor layer completely encircling mask portions of insulating material, wherein said semiconductor layer is surrounded by an oxide layer;

d) a structural layer extending on top of said body and said diaphragm;

e) a reservoir layer extending on top of said structural layer and a first reservoir extending through said reservoir layer as far as said structural layer; and

f) a first aperture extending through said structural layer and connecting said first reservoir with said channel.

2. The integrated microreactor of claim 1, wherein said channel has a width ≧

200 μ

m.

3. The integrated microreactor of claim 2, wherein said channel has a width between 200 μ

m and 500 μ

m.

4. The integrated microreactor of claim 2, further comprising:

a) a second reservoir extending through said reservoir layer as far as said structural layer; and

;

b) a second aperture extending through said structural layer and connecting said second reservoir with said channel.

5. The integrated microreactor of claim 2, wherein said body is of monocrystalline silicon and said coating layer is of oxide.

6. The integrated microreactor of claim 4, wherein said body is of monocrystalline silicon and said coating layer is of oxide.

7. The integrated microreactor of claim 6, wherein said structural layer is a psuedo epitaxial layer.

16. A method of performing a biological test, wherein a biological fluid is applied to the integrated microreactor of any one of claims 1-7 and a biological test is performed.

17. The method of claim 16, wherein the biological test is amplification.

18. The method of claim 17, wherein the amplification is DNA amplification.

8. A process for manufacturing an integrated microreactor, comprising the steps of:

a) forming a body of semiconductor material;

b) forming a mask of insulating material on top of said body, said mask having a plurality of openings;

c) etching said body using said mask to form a channel having walls;

d) forming, on top of said body, a diaphragm extending over said channel by depositing a semiconductor layer completely surrounding and filling said openings;

e) forming a structural layer on top of said body and said diaphragm;

f) forming a hole in said structural layer and said diaphragm as far as said channel; and

g) forming a coating layer of insulating material coating said walls, wherein said coating layer is added through said hole.

9. The process of claim 8, said channel has a width ≧

200 μ

m.

10. The process of claim 9, wherein said mask has a grid-like shape.

11. The process of claim 10, wherein forming a coating layer comprises thermally oxidizing said walls.

12. The process of claim 11, wherein forming a coating layer comprises depositing semiconductor portions coating said walls and thermally oxidizing said semiconductor portions.

13. The process of claim 12, wherein said mask further includes an oxidation opening having larger dimensions than said plurality of openings so that said oxidation opening is not filled by said semiconductor layer during depositing a semiconductor layer.

14. The process of claim 13, further comprising forming heating elements and electrode elements above said structural layer;

and forming an inlet and an outlet opening extending through said structural layer as far as said channel.

15. The process of claim 14, further comprising forming an upper layer on top of said structural layer and forming a first and a second reservoir extending through said upper layer and in contact with said inlet and outlet openings.