Semiconductor device and method for manufacturing the semiconductor device

• US 20070252233A1
• Filed: 04/16/2007
• Published: 11/01/2007
• Est. Priority Date: 04/28/2006
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kawamata, Ikuko, Arai, Yasuyuki, Yamazaki, Shunpei
• Application Number:
  US11/785,150
• Publication Number:
  US 20070252233A1
• Time in Patent Office: Days
• US Class Current: 257/504
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Abstract

A semiconductor device is provided, which comprises a semiconductor layer over an insulating surface, and an insulating layer over the semiconductor layer. The semiconductor layer includes at least two element regions, and an element separation region. The element separation region is disposed between the two element regions. The element separation region includes at least one impurity element selected from the group consisting of oxygen, nitrogen, and carbon. The element separation region has higher resistance than a first source and drain regions included in one of the two element regions and a second source and drain regions included in the other of the two element regions.

Claims

1. A semiconductor device comprising:

a semiconductor layer over an insulating surface, the semiconductor layer includes at least two element regions, and an element separation region, and

an insulating layer over the semiconductor layer,

wherein;

the element separation region is disposed between the two element regions,

the element separation region includes at least one impurity element selected from the group consisting of oxygen, nitrogen, and carbon, and

the element separation region has higher resistance than a first source and drain regions included in one of the two element regions and a second source and drain regions included in the other of the two element regions.

2. The semiconductor device according to claim 1, further includes at least a gate electrode over the insulating layer, and wherein the gate electrode overlaps with the one of the two element regions.

3. The semiconductor device according to claim 1, wherein a surface of the semiconductor layer is a plane surface.

4. The semiconductor device according to claim 1, wherein the first source and drain regions and the second source and drain regions are electrically insulated by the element separation region.

5. The semiconductor device according to claim 1, wherein concentration of the impurity element included in the element separartion region is greater than or equal to 1×

10²⁰ cm<sup>−

3</sup> and less than 4×

10²² cm<sup>−

3</sup>.

6. The semiconductor device according to claim 1, wherein resistivity of the element separation region is greater than or equal to 1×

10¹⁰ Ω

·

cm.

7. The semiconductor device according to claim 1, wherein the element separation region further includes a rare gas element.

8. A semiconductor device comprising:

a semiconductor layer over an insulating surface, the semiconductor layer includes at least two element regions, and an element separation region, and

an insulating layer over the semiconductor layer,

wherein;

the element separation region is disposed between the two element regions,

the element separation region includes at least one impurity element selected from the group consisting of oxygen, nitrogen, and carbon,

the element separation region has higher resistance than a first source and drain regions included in one of the two element regions and a second source and drain regions included in the other of the two element regions, and

the element separation region has lower crystallinity than a first channel formation region included in the one of the two element regions and a second channel formation region included in the other of the two element regions.

9. The semiconductor device according to claim 8, further includes at least a gate electrode over the insulating layer, and wherein the gate electrode overlaps with the one of the two element regions.

10. The semiconductor device according to claim 8, wherein a surface of the semiconductor layer is a plane surface.

11. The semiconductor device according to claim 8, wherein the first source and drain regions and the second source and drain regions are electrically insulated by the element separation region.

12. The semiconductor device according to claim 8, wherein concentration of the impurity element included in the element separartion region is greater than or equal to 1×

10²⁰ cm<sup>−

3</sup> and less than 4×

10²² cm<sup>−

3</sup>.

13. The semiconductor device according to claim 8, wherein resistivity of the element separation region is greater than or equal to 1×

10¹⁰ Ω

·

cm.

14. The semiconductor device according to claim 8, wherein the element separation region further includes a rare gas element.

15. A method of manufacturing a semiconductor device comprising the steps of:

forming a semiconductor layer over an insulating surface,

forming at least two element regions and an element separation region in the semiconductor layer by selectively adding at least one impurity element selected from the group consisting of oxygen, nitrogen, and carbon, and

forming an insulating layer over the semiconducor layer.

16. The method of manufacturing a semiconductor device according to claim 15, further includes a step of forming at least a gate electrode over the insulating layer, and wherein the gate electrode overlaps with the one of the two element regions.

17. The method of manufacturing a semiconductor device according to claim 15, wherein a surface of the semiconductor layer is a plane surface.

18. The method of manufacturing a semiconductor device according to claim 15, wherein the first source and drain regions and the second source and drain regions are electrically insulated by the element separation region.

19. The method of manufacturing a semiconductor device according to claim 15, wherein concentration of the impurity element included in the element separartion region is greater than or equal to 1×

10²⁰ cm<sup>−

3</sup> and less than 4×

10²² cm<sup>−

3</sup>.

20. The method of manufacturing a semiconductor device according to claim 15, wherein resistivity of the element separation region is greater than or equal to 1×

101 Ω

·

cm.

21. The method of manufacturing a semiconductor device according to claim 15, wherein the element separation region further includes a rare gas element.