Power Semiconductor Module As H - Bridge Circuit And Method For Producing The Same

• US 20070252265A1
• Filed: 04/26/2007
• Published: 11/01/2007
• Est. Priority Date: 04/27/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Sander, Rainald
• Granted Patent: US 7,449,778 B2
• Time in Patent Office: Days
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/37599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/8485 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/39 Structure, shape, material or disposition of the strap connectors after the connecting process
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

A power semiconductor module (41) as H-bridge circuit (42) has four power semiconductor chips (N1, N2, P1, P2) and a semiconductor control chip (IC). The semiconductor chips (N1, N2, P1, P2, IC) are arranged on three mutually separate large-area lead chip contact areas (43 to 45) of a lead plane (80). The semiconductor control chip (IC) is arranged on a centrally arranged lead chip contact area (45). An n-channel power semiconductor chip (N1, N2) as low-side switch (58, 59) and a p-channel power semiconductor chip (P1, P2) as high-side switch (48, 49) are in each case arranged on two laterally arranged lead chip contact areas (43, 44). The n-channel power semiconductor chips (N1, N2) are jointly at an earth potential (50) and the p-channel power semiconductor chips (P1, P2) are electrically connected to separate supply voltage sources (VS1, VS2).

Claims

1. A power semiconductor module as H-bridge circuit comprising four power semiconductor chips and a semiconductor control chip, the semiconductor chips being arranged on three mutually separate large-area lead chip contact areas of a lead plane, having a centrally arranged lead chip contact area, on which the semiconductor control chip is arranged, and two laterally arranged lead chip contact areas, on each of which are arranged an n-channel power semiconductor chip as low-side switch and a p-channel power semiconductor chip as high-side switch, and the n-channel power semiconductor chips being jointly electrically connected to an earth potential and the p-channel power semiconductor chips being electrically connected to separate supply voltage sources.

2. The power semiconductor module according to claim 1, wherein contact areas on the top sides of the semiconductor chips are electrically connected via individual bonding wires for control signal transfer between the central semiconductor control chip and the four laterally arranged power semiconductor chips.

3. The power semiconductor module according to claim 1, wherein large-area contact areas on the top sides of the power semiconductor chips are connected via a multiplicity of parallel bonding wires to a respective one of the large-area lead contact areas on the lead plane.

4. The power semiconductor module according to claim 1, wherein large-area contact areas on the top sides of the power semiconductor chips are connected via bonding tapes to a respective large-area lead contact area on the lead plane.

5. The power semiconductor module according to claim 1, wherein large-area contact areas on the top sides of the power semiconductor chips are connected via conductor clips to a respective large-area lead contact area on the lead plane.

6. The power semiconductor module according to claim 1, wherein the power semiconductor module has leads arranged in a plane as surface-mountable external contacts on the underside of the power semiconductor module, which merge into edge side contacts on the edge sides.

7. The power semiconductor module according to claim 1, wherein the power semiconductor module comprises 36 edge side contacts, a first output terminal comprising the edge side contacts 1 to 4 and 33 to 36, a second output terminal comprising the edge side contacts 15 to 18 and 19 to 22, a first supply terminal comprising the edge side contacts 29 to 32, a second supply terminal comprising the edge side contacts 11 to 14 and an earth terminal comprising the edge side contacts 5 to 8 and 23 to 26, while the edge side contacts 9 and 11 and 27 and 28 are signal external terminals.

8. The power semiconductor module according to claim 1, wherein the power semiconductor module comprises FET transistors as power semiconductor chips.

9. The power semiconductor module according to claim 1, wherein the low-side switches are cohesively and electrically conductively connected by their source contacts and gate contacts respectively to an output terminal on the respective lead chip contact areas.

10. The power semiconductor module according to claim 1, wherein the low-side switches are electrically connected by their drain contacts to the earth terminal via connecting elements and via the central lead chip contact area.

11. The power semiconductor module according to claim 1, wherein the high-side switches are cohesively and electrically conductively connected by their drain contacts respectively to an output terminal on the respective lead chip contact areas.

12. The power semiconductor module according to claim 1, wherein the high-side switches are cohesively and electrically conductively connected by their source contacts via connecting elements respectively to a supply voltage terminal on the respective lead external contacts.

13. The power semiconductor module according to claim 1, wherein contact areas of the semiconductor control chip are connected via bonding wire connections to the gate contacts and the source contacts of the high-side switches, and also to the drain contacts of the low-side switches.

14. The power semiconductor module according to claim 1, wherein contact areas of the semiconductor control chip are connected via bonding wire connections to signal external contacts of the power semiconductor module.

15. The power semiconductor module according to claim 1, wherein the external contacts of the power semiconductor module are a planar structured lead plate of a leadframe.

16. The power semiconductor module according to claim 1, wherein the power semiconductor module comprises a housing composed of a plastic housing composition, into which are embedded the power semiconductor chips, the semiconductor control chip, the connecting elements and the external contacts whilst leaving free external and edge contact areas on the underside and the edge sides of the power semiconductor module.

17. A method for producing a plurality of power semiconductor modules as H-bridge circuit having four power semiconductor chips and a semiconductor control chip, the method having the following method steps:

producing a leadframe having a plurality of power semiconductor module positions, three large-area lead chip contact areas and two lead contact areas for supply terminals and four lead contact areas for control signal terminals being arranged in the power semiconductor module positions, the first large-area lead chip contact area being provided for an n-channel power semiconductor chip as low-side switch and for a p-channel power semiconductor chip as high-side switch of the first half-bridge and the second lead chip contact area being provided for the power semiconductor chips of the second half-bridge of the H-bridge circuit and the third lead contact area being provided for the semiconductor control chip with earth terminal;

applying the power semiconductor chips and the semiconductor control chip to the provided large-area lead contact areas of the leadframe;

fitting of connecting elements between contact areas of the semiconductor chips (N1, N2, P1, P2, IC) and the lead contact areas, and also between contact areas of the semiconductor chips (N1, N2, P1, P2, IC) among one another;

packaging of the power semiconductor chips and the connecting elements, and also the lead contact areas into a plastic housing composition whilst leaving free external contact areas of the lead terminals of the leadframe;

separating the leadframe into individual power semiconductor modules.

18. The method according to claim 17, wherein a metal plate, preferably a planar copper plate, is structured for the production of a leadframe.

19. The method according to claim 18, wherein the planar metal plate is stamped for the structuring.

20. The method according to claim 18, wherein the planar metal plate is subjected to wet or dry etching for the structuring.

21. The method according to claim 17, wherein for the production of a leadframe, the leadframe structure is electrodeposited on an auxiliary carrier and is subsequently detached from the auxiliary carrier.

22. The method according to claim 17, wherein

during the application of the power semiconductor chips and the semiconductor control chip to the large-area lead chip contact areas provided, the chips are soldered or adhesively bonded onto the lead contact areas.

23. The method according to claim 17, wherein bonding wire connections are produced during the fitting of connecting elements between contact areas at the semiconductor control chip and the lead contact areas and also between contact areas of the semiconductor control chip and contact areas of the power semiconductor chips.

24. The method according to claim 17, wherein multiple bonding wire connections or bonding clips, preferably bonding tapes are used during the fitting of connecting elements between contact areas of the power semiconductor chips and the lead contact areas.

25. The method according to claim 17, wherein a stamping method is used for the separation of the leadframe into individual power semiconductor modules.

26. The method according to claim 17, wherein an etching method is used for the separation of the leadframe into individual power semiconductor modules.