GRAY SCALE DRIVE SEQUENCES FOR PULSE WIDTH MODULATED DISPLAYS

• US 20070252856A1
• Filed: 04/25/2007
• Published: 11/01/2007
• Est. Priority Date: 04/27/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Jasper Display Corp.
• Inventors: HUDSON, EDWIN, Cowl, David
• Granted Patent: US 8,111,271 B2
• Time in Patent Office: Days
• US Class Current: 345/693
• CPC Class Codes: G09G 2320/0673 for control of gamma adjustment, e.g. selecting another gamma curve
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2025 the sub-frames having all the same time duration
• CPC Class Codes: G09G 3/2029 the sub-frames having non-binary weights
• CPC Class Codes: G09G 3/2033 with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/2037 with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/204 the sub-frames being organized in consecutive sub-frame groups

Abstract

Methods, apparatus, and systems for generating drive sequences for pulse width modulated displays are described. A pulse width modulated signal that includes a drive sequence of temporal segments that are activated and deactivated to produce a desired gray scale. The temporal segments can be non-binary, non-equally weighted. The drive sequence can also include at least two of the temporal segments are least significant bit segments and the other segments are higher order segments.

Claims

1. A method for providing a drive sequence for a pulse width modulated display, the method comprising:

determining a set of non-binary, non-equal, weighted temporal segments;

assembling the set of segments into a sequence;

identifying segments in the sequence that are active; and

using the sequence to pulse width modulate pixels in a display, wherein a pixel'"'"'s brightness corresponds to the number of active temporal segments in the sequence.

2. The method of claim 1, wherein higher order segments increase in weighting monotonically.

3. The method of claim 1, wherein the weighting of the segments is adjusted to produce a gray scale output corresponding to the number of active segments in the sequence that simulates a gamma curve.

4. The method of claim 1, wherein the sequence comprises at least two least significant bit segments.

5. The method of claim 4, wherein the at least two least significant bit segments are not adjacent to each other.

6. The method of claim 1, wherein the temporal activation of the segments is discontinuous.

7. The method of claim 1, wherein the sequence comprises non-contiguous time slots.

8. A display comprising:

a plurality of pixels;

a voltage controller that provides at least one voltage supply that is applied to the pixels in the display; and

a processor that receives image data and determines a set of non-binary, non-equal, weighted temporal segments based on the image data, and assembles the set of segments into a sequence, wherein selected segments are activated in accordance with a desired brightness level of pixels within the display and the sequence includes at least two least significant bit segments.

9. The display of claim 8, wherein higher order segments increase in weighting monotonically.

10. The display of claim 8, wherein the at least two least significant bit segments are not adjacent to each other.

11. The display of claim 8, wherein the temporal activation of the segments is discontinuous.

12. The display of claim 8, wherein the sequence comprises non-contiguous time slots.

13. The display of claim 8, wherein the pixels comprise liquid crystal on silicon elements.

14. The display of claim 8, wherein the image data comprises a gray scale command.

15. The display of claim 8, wherein the image data comprises multiple color image data.

16. The display of claim 8, wherein the image data is formatted as a digital video interface (DVI) signal.

17. The display of claim 8, wherein the image data is formatted as a high definition multimedia interface (HDMI) signal.

18. A controller for a pulse width modulated display, the controller comprising:

a voltage controller that provides at least one voltage supply that is applied to pixels in a display; and

a processor that receives image data and determines a set of non-binary, non-equal, weighted temporal segments based on the image data, and assembles the set of segments into a sequence, wherein selected segments are activated in accordance with a desired brightness level of pixels within the display and the sequence includes at least two least significant bit segments.

19. The controller of claim 18, wherein higher order segments increase in weighting monotonically.

20. The controller of claim 18, wherein the at least two least significant bit segments are not adjacent to each other.

21. The controller of claim 18, wherein the temporal activation of the segments is discontinuous.

22. The controller of claim 18, wherein the sequence comprises non-contiguous time slots.

23. The controller of claim 18, wherein the pixels comprise liquid crystal on silicon elements.

24. The controller of claim 18, wherein the image data comprises a gray scale command.

25. The controller of claim 18, wherein the image data comprises multiple color image data.

26. The controller of claim 18, wherein the image data is formatted as a digital video interface (DVI) signal.

27. The controller of claim 18, wherein the image data is formatted as a high definition multimedia interface (HDMI) signal.