System and methods for the simultaneous display of multiple video signals in high definition format

• US 20070252912A1
• Filed: 04/24/2007
• Published: 11/01/2007
• Est. Priority Date: 04/24/2006
• Status: Active Grant

• Current Assignee: Geno Valente, Mary Beth Valente
• Original Assignee: Geno Valente, Mary Beth Valente
• Inventors: Valente, Mary Beth, Valente, Geno
• Granted Patent: US 8,350,961 B2
• Time in Patent Office: Days
• US Class Current: 348/458
• CPC Class Codes: H04N 21/25 Management operations performed by the server for facilitating the content distribution or administrating data related to end-users or client devices, e.g. end-user or client device authentication, learning user preferences for recommending movies maintenance or administration in data networks H04L41/00
• CPC Class Codes: H04N 21/4122 additional display device, e.g. video projector digital output for controlling a plurality of local displays G06F3/1423
• CPC Class Codes: H04N 21/4316 for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/43635 HDMI
• CPC Class Codes: H04N 21/440263 by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4622 Retrieving content or additional data from different sources, e.g. from a broadcast channel and the Internet web site content organization and management for information retrieval from the Internet G06F16/958; transmission by internet of broadcast information H04H60/82; stock exchange data over packet-switching network H04L12/1804; push services including data channel over packet-switching network H04L12/1859
• CPC Class Codes: H04N 21/47 End-user applications
• CPC Class Codes: H04N 21/4781 Games
• CPC Class Codes: H04N 21/4782 Web browsing , e.g. WebTV
• CPC Class Codes: H04N 21/4788 communicating with other users, e.g. chatting arrangements for providing for computer conferences, e.g. chat rooms, to substation in data switching networks H04L12/1813; distributed application using peer-to-peer [P2P] networks H04L67/104
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 7/0125 one of the standards being a high definition standard
• CPC Class Codes: H04N 7/0806 the signals being two or more video signals H04N7/0803, H04N7/081 take precedence

Abstract

A scaling engine, blending mechanism, memory controller, frame buffer and video driver are included within a semiconductor, such as a Field Programmable Gate Array (FPGA), to provide broadcasting of signals at a high resolution format by combining two or more low resolution video signals to create a high resolution signal in real-time High Definition format, such as 1080p. The high resolution signals can be concurrently displayed as one or more image areas on a display device in any contemplated size, number and arrangement.

Claims

1. A method of displaying video signals in high definition format, comprising:

receiving two or more low resolution video signals;

manipulating the two or more video signals;

blending the two or more video signals;

assembling the two or more video signals into a frame buffer;

reading the frame buffer;

formatting the two or more video signals of the frame buffer into a high resolution video signal;

sending the high resolution video signal over an interface;

illustrating the high resolution video signal as an image area on a display device.

2. The method of claim 1, wherein the step of blending the two or more video signals further comprises changing the transparency of the video signals.

3. The method of claim 1, wherein the low resolution video signals are 720p format.

4. The method of claim 1, wherein the high resolution video signal is 1080p format.

5. The method of claim 1, wherein the step of illustrating the image area further comprises concurrently illustrating two or more image areas on the display device.

6. A system to simultaneously display one or more video signal in high definition format, comprising:

an input device, wherein said input device transmits two or more low resolution video signals;

a scaling engine, wherein said scaling engine manipulates said two or more low resolution video signals;

a blending mechanism, wherein said blending mechanism blends said manipulated video signal;

a memory controller, wherein said memory controller receives said blended video signal;

a frame buffer, wherein said frame buffer includes data regarding said blended video signal;

a video driver, wherein said video driver reads and formats the blended video signal;

an interface, wherein said interface provides a high resolution video signal; and

a display device, wherein said display device illustrates said high resolution video signal as an image area.

7. The system of claim 6, wherein said blending mechanism includes alpha blending.

8. The system of claim 6, wherein said memory controller assembles said blended video signals within said frame buffer.

9. The system of claim 6, wherein said scaling engine, said blending mechanism, said memory controller, said frame buffer and said video driver are packaged within a semiconductor.

10. The system of claim 9, wherein said semiconductor is a Field Programmable Gate Array (FPGA).

11. The system of claim 6, wherein said low resolution video signals are 720p format.

12. The system of claim 6, wherein said high resolution video signal is 1080p format.