Method for programming a reference cell

• US 20070253248A1
• Filed: 09/11/2006
• Published: 11/01/2007
• Est. Priority Date: 04/27/2006
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Maayan, Eduardo, Lann, Ameet
• Granted Patent: US 7,701,779 B2
• Time in Patent Office: Days
• US Class Current: 365/185.200
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.

Claims

1. A method of programming a set of reference cells, wherein each reference cell is associated with a separate set of non-volatile memory cells, said method comprising:

programming a first reference cell within the set of reference cells as a function of a native threshold voltage distribution of a first set of non-volatile memory cells; and

programming a second reference cell as a function of a native threshold voltage distribution of a second set of non-volatile memory cells.

2. The method according to claim 1, further comprising programming a second set of reference cells such that a reference cell in the second set is programmed as a function of a threshold voltage of a cell in the first set of reference cells.

3. The method according to claim 1, wherein the first reference cell is programmed to a threshold voltage substantially correlated with a highest native threshold voltage of a non-volatile memory cell in the first set of non-volatile memory cells.

4. The method according to claim 3, wherein the first reference cell is programmed to a threshold voltage at a predefined offset above a highest native threshold voltage of a non-volatile memory cell in the first set of non-volatile memory cells.

5. The method according to claim 3, wherein the second reference cell is programmed to a threshold voltage substantially correlated with a highest native threshold voltage of a non-volatile memory cell in the second set of nonvolatile memory cells.

6. The method according to claim 5, wherein the second reference cell is programmed to a threshold voltage at a predefined offset above a highest native threshold voltage of a nonvolatile memory cell in the second set of non-volatile memory cells.

7. The method according to claim 6, further comprising programming a third reference cell as a function of a native threshold voltage distribution of a third set of non-volatile memory cells.

8. A non-volatile memory device comprising:

two or more sets of non-volatile memory cells; and

a first set of reference cells, wherein each reference cell is associated with a separate set of non-volatile memory cells and programmed as a function of a native threshold voltage distribution of the set of non-volatile memory cells with which it is associated.

9. The non-volatile memory device of claim 8 further comprising a second set of reference cells such that a reference cell in said second set is programmed as a function of a threshold voltage of a cell in said first set of reference cells.

10. The device according to claim 8, wherein the first reference cell is programmed to a threshold voltage substantially correlated with a highest native threshold voltage of a non-volatile memory cell in the first set of nonvolatile memory cells.

11. The method according to claim 10, wherein the first reference cell is programmed to a threshold voltage at a predefined offset above a highest native threshold voltage of a non-volatile memory cell in the first set of non-volatile memory cells.

12. The method according to claim 10, wherein the second reference cell is programmed to a threshold voltage substantially correlated with a highest native threshold voltage of a non-volatile memory cell in the second set of non-volatile memory cells.

13. The method according to claim 12, wherein the second reference cell is programmed to a threshold voltage at a predefined offset above a highest native threshold voltage of a non-volatile memory cell in the second set of non-volatile memory cells.

14. The method according to claim 13, further comprising programming a third reference cell as a function of a native threshold voltage distribution of a third set of non-volatile memory cells.

15. A non-volatile memory device comprising:

two or more sets of non-volatile memory cells; and

a first set of reference cells, wherein each reference cell is associated with a separate set of non-volatile memory cells and wherein a majority of reference cells are programmed at a threshold voltage different from one another.

16. The non-volatile memory device of claim 15 further comprising a second set of reference cells such that a reference cell in said second set is programmed as a function of a threshold voltage of a cell in said first set of reference cells.

17. A non-volatile memory device comprising at least one set of non-volatile memory cells;

and

a set of reference cells, wherein at least one reference cell is programmed as a function of a native threshold voltage distribution of at least one set of nonvolatile memory cells.

18. The non-volatile memory device of claim 17, wherein at least one reference cell in said set of reference cells is programmed as a function of a threshold voltage of another reference cell in said set of reference cells.

19. A non-volatile memory device comprising at least one set of nonvolatile memory cells;

and

a set of reference cells, wherein at least two of the reference cells in the set are programmed to different levels.

20. The nonvolatile memory device of claim 19, wherein said different levels are a function of the native threshold voltage distribution of said at least one set of non-volatile memory cells.

21. The non-volatile memory device of claim 19, wherein said different levels may be detected by measuring the voltage or current signals generated by said at least two of the reference cells.