Memory voltage cycle adjustment

• US 20070253256A1
• Filed: 05/01/2006
• Published: 11/01/2007
• Est. Priority Date: 05/01/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Granted Patent: US 7,495,966 B2
• Time in Patent Office: Days
• US Class Current: 365/185.240
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices

Abstract

The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles.

Claims

1. A method comprising;

counting a number of process cycles performed on a first memory block in a memory device; and

adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles.

2. The method of claim 1 wherein adjusting a number of program voltages is accomplished by decreasing each of the number of program voltages.

3. The method of claim 1 wherein adjusting a number of program voltages is accomplished by decreasing each of the number of program voltages as the counted number of process cycles for the memory block increases.

4. The method of claim 1 wherein adjusting a number of program voltages is accomplished by decreasing each of the number of program voltages periodically as the counted number of process cycles for the memory block increases past a number of process cycle count thresholds.

5. A method comprising;

counting a number of program/erase cycles performed on a first memory block in a memory device having a memory array comprising a plurality of memory blocks, each memory block having a plurality of memory cells arranged in rows that are coupled by word lines; and

adjusting a number of program voltages, from an initial program voltage, over time in response to the counted number of program/erase cycles.

6. The method of claim 5 wherein adjusting the number of program voltages is accomplished periodically based upon a number of program/erase cycle count thresholds.

7. The method of claim 5 wherein the number of program voltages are a number of stepped voltages.

8. The method of claim 5 wherein the number of program voltages are in a range of 16-20V.

9. The method of claim 5 wherein the number of adjusted program voltages are in a range of 14-19V.

10. The method of claim 5 wherein adjusting a number of program voltages, from an initial program voltage, over time in response to the counted number of program/erase cycles is accomplished by decreasing at least one of the number of program voltages.

11. A method comprising;

counting a number of program/erase cycles performed on a first memory block in a memory device having a memory array comprising a plurality of memory blocks, each memory block having a plurality of memory cells arranged in rows that are coupled by word lines; and

decreasing each of a number of stepped program voltages, from an initial program voltage, in response to the count of program/erase cycles.

12. The method of claim 11 wherein decreasing each of a number of stepped program voltages, from an initial program voltage, in response to the counted number of program/erase cycles is accomplished by decreasing each of the number of program voltages by 0.6V.

13. The method of claim 11 wherein decreasing each of a number of stepped program voltages, from an initial program voltage, in response to the counted number of program/erase cycles is accomplished by decreasing each of a number of stepped program voltages as the count of program/erase cycles for the memory block increases.

14. The method of claim 11 wherein decreasing each of a number of stepped program voltages, from an initial program voltage, in response to the counted number of program/erase cycles is accomplished by decreasing each of a number of stepped program voltages as the count of program/erase cycles for the memory block increases, wherein an increase to a larger program voltage is greater than an increase to a smaller program voltage.

15. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and

control circuitry coupled to the array of non-volatile memory cells and adapted to execute a method for programming that includes;

generating an initial programming voltage;

counting a quantity of program/erase cycles; and

decreasing the programming voltage based upon the quantity of program/erase cycles.

16. The device of claim 15 wherein the control circuitry is programmed to decrease the program voltage by a particular voltage amount each time the count reaches a predetermined quantity of program/erase cycles.

17. The device of claim 15 wherein the control circuitry is programmed to decrease the program voltage by a particular voltage amount each time the count reaches a quantity of 1,000 program/erase cycles.

18. The device of claim 15 wherein the control circuitry is programmed to decrease a first program voltage by a first voltage amount and a second program voltage by a second voltage amount.

19. The device of claim 15 wherein the control circuitry is programmed to decrease a first program voltage at a first time and a second program voltage at a second time.

20. The device of claim 15 wherein the control circuitry is programmed to decrease a first program voltage by a particular voltage amount when the count reaches a first predetermined quantity of program/erase cycles and decrease a second program voltage by a particular voltage amount when the count reaches a second predetermined quantity of program/erase cycles.

21. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and

control circuitry coupled to the array of non-volatile memory cells and adapted to execute a method for programming that includes;

generating an initial programming voltage;

counting a quantity of program/erase cycles;

decreasing a first program voltage by a first voltage amount when the quantity of program/erase cycles reaches a first predetermined quantity of program/erase cycles; and

decreasing a second program voltage by a second voltage amount when the quantity of program/erase cycles reaches a second predetermined quantity of program/erase cycles.

22. The device of claim 21 wherein the first and second predetermined quantities of program/erase cycles are different.

23. The device of claim 21 wherein the first and second voltage amounts are different.

24. The device of claim 21 wherein the first and second predetermined quantities of program/erase cycles are different and the first and second voltage amounts are different.

25. The device of claim 21 wherein the first and second program voltages are pulsed program voltages, and wherein a step up voltage associated with the first program voltage is the same as a step up voltage associated with the second program voltage.

26. The device of claim 21 wherein the array of non-volatile memory cells is arranged in a NOR architecture.

27. A memory system comprising:

a processor for generating memory control signals;

a flash memory device coupled to the processor, the device comprising memory cell array arranged in rows and columns; and

control circuitry for controlling a number of program voltages during a program operation wherein the control circuitry is adapted to adjust at least one of the program voltages, from an initial program voltage to an adjusted program voltage in response to a cycle count.

28. The system of claim 27 wherein the control circuitry for controlling a number of program voltages during a program operation wherein the control circuitry is adapted to adjust at least one of the program voltages, from an initial program voltage to an adjusted program voltage in response to a program cycle count.

29. The system of claim 27 wherein the control circuitry for controlling a number of program voltages during a program operation wherein the control circuitry is adapted to adjust at least one of the program voltages, from an initial program voltage to an adjusted program voltage in response to a erase cycle count.

30. A memory module comprising:

a memory device comprising;

a memory cell array arranged in rows and columns;

control circuitry for controlling a number of program voltages to adjust at least one of the program voltages, from an initial program voltage to an adjusted program voltage in response to a cycle count; and

a plurality of contacts configured to provide selective contact between the memory device and a host system.

31. The module of claim 30 and further including a memory controller coupled to the memory device for controlling operation of the memory device in response to the host system.

32. The module of claim 30 wherein the plurality of non-volatile memory cells are flash memory cells.

33. A method comprising;

counting a number of process cycles performed on a first memory block in a memory device; and

adjusting a difference between a program verify voltage and a read voltage associated with the number of process cycles, from an initial voltage difference, in response to the counted number of process cycles.

34. The method of claim 33, wherein adjusting a difference between a program verify voltage and a read voltage includes increasing the difference from the initial voltage difference as the number of process cycles for the memory block increases.

35. The method of claim 33, wherein the method includes increasing the read voltage from an initial read voltage value in response to the counted number of process cycles.

36. The method of claim 33, wherein adjusting a difference between a program verify voltage and a read voltage includes increasing the difference from the initial voltage difference periodically as the number of process cycles for the memory block increases past a number of process cycle count thresholds.

37. The method of claim 36, wherein increasing the difference from the initial voltage difference includes increasing the difference by about 100 mV.

38. The method of claim 33, wherein counting a number of processing cycles performed on a first memory block includes counting a number of program/erase cycles performed on the memory block, and wherein the memory device includes a memory array comprising a plurality of memory blocks, each memory block having a plurality of memory cells arranged in rows that are coupled by word lines.

39. The method of claim 33, wherein the initial voltage difference is in the range of 100-200 mV.

40. The method of claim 33, wherein the memory device is a flash memory device, and wherein the memory block comprises multiple level memory cells (MLCs).

41. A method comprising;

counting a number of program/erase cycles performed on a first memory block in a memory device having a memory array comprising a plurality of memory blocks, each memory block having a plurality of multiple level memory cells (MLCs) arranged in rows that are coupled by word lines, and each MLC capable of being programmed to an erased level and capable of being programmed to at least a first program level and a second program level, the second program level being higher than the first; and

adjusting a difference between a program verify voltage and a corresponding read voltage associated with at least one of the first program level and second program level of at least one of the plurality of MLCs, from an initial voltage difference, in response to the counted number of program/erase cycles.

42. The method of claim 41, wherein each of the program levels has a different program verify voltage and read voltage associated therewith, and wherein adjusting a difference between a program verify voltage and a corresponding read voltage includes adjusting the difference between the program verify voltage and corresponding read voltage associated with each one of the program levels of at least one of the plurality of MLCs, from an initial voltage difference, in response to the counted number of program/erase cycles.

43. The method of claim 41, wherein adjusting a difference between a program verify voltage and a corresponding read voltage associated with at least one of the first program level and second program level of at least one of the plurality of MLCs includes increasing the difference, from the initial voltage difference, when the counted number of program/erase cycles reaches a threshold value.

44. The method of claim 43, wherein increasing the difference, from the initial voltage difference, includes increasing the difference associated with the first program level at a threshold value that is different than a threshold value at which the difference associated with the second program level is increased.

45. The method of claim 43, wherein the second program level corresponds to a higher state of the MLC than the first program level and increasing the difference, from the initial voltage difference, includes increasing the difference associated with the second program level by a greater amount than the first program level.

46. The method of claim 45, wherein the initial voltage difference associated with the first program level is in the range of 0.1-0.15V and the initial voltage difference associated with the second program level is in the range of 0.16-0.3V, and wherein increasing the difference associated with the second level includes increasing the difference by about 0.5V.

47. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and

control circuitry coupled to the array of non-volatile memory cells and adapted to execute a method for programming the array that includes;

generating an initial program verify voltage;

generating an initial read voltage;

counting a quantity of program/erase cycles performed on the array; and

increasing a difference between the initial program verify voltage and the initial read voltage based upon the quantity of program/erase cycles.

48. The device of claim 47, wherein the control circuitry is programmed to increase the difference each time the counted quantity reaches a predetermined value of program/erase cycles.

49. The device of claim 47, wherein the control circuitry is programmed to increase the difference by a particular voltage amount each time the counted quantity reaches 1,000 program/erase cycles.

50. The device of claim 47, wherein the control circuitry is programmed to increase the initial read voltage based upon the quantity of program/erase cycles.

51. The device of claim 47, wherein the non-volatile memory cells are multiple level cells (MLCs) having a plurality of program states, and wherein the control circuitry is programmed to:

generate an initial program verify voltage for each of the plurality of program states;

generate an initial read voltage for each of the plurality of program states; and

increase a difference between the initial program verify voltage and the initial read voltage of each of the plurality of program states.

52. The device of claim 51, wherein the control circuitry is programmed to increase a difference between the initial program verify and read voltage of a first program state by an amount different from an increase in a difference between the initial program verify and read voltage of a second program state.

53. The device of claim 51, wherein the control circuitry is programmed to:

increase a difference between the initial program verify and read voltage of a first program state after a first quantity of program/erase cycles; and

increase a difference between the initial program verify and read voltage of a second program state after a second quantity of program/erase cycles.

54. The device of claim 47, wherein the array of non-volatile memory cells is arranged in a NAND architecture.

55. A memory system comprising:

a processor for generating memory control signals;

a flash memory device coupled to the processor, the device comprising;

a memory cell array arranged in rows and columns; and

control circuitry for controlling a number of program verify voltages and a number of read voltages during a program operation wherein the control circuitry is adapted to adjust a difference between at least one of the number program verify voltages and at least one of the number of read voltages, from an initial voltage difference to an adjusted voltage difference based on a count of processing cycles performed on the array.

56. The system of claim 56, wherein the control circuitry for controlling a number of program verify voltages and a number of read voltages during a program operation is adapted to increase the difference between at least one of the number program verify voltages and at least one of the number of read voltages, from the initial voltage difference to the adjusted voltage difference based on a count of programming/erase cycles performed on the array.

57. A memory module comprising:

a memory device comprising;

a memory cell array arranged in rows and columns;

control circuitry for controlling a number of program verify voltages and a number of read voltages during a program operation wherein the control circuitry is adapted to increase a difference between at least one of the number program verify voltages and at least one of the number of read voltages, from an initial voltage difference to an adjusted voltage difference based on a count of program/erase cycles performed on the array; and

a plurality of contacts configured to provide selective contact between the memory device and a host system.

58. The module of claim 57, and further including a memory controller coupled to the memory device for controlling operation of the memory device in response to the host system.

59. The module of claim 57, wherein the plurality of non-volatile memory cells are flash memory cells.