METHOD AND APPARATUS FOR ON-CHIP DUTY CYCLE MEASUREMENT

• US 20070255517A1
• Filed: 05/01/2006
• Published: 11/01/2007
• Est. Priority Date: 05/01/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Qi, Jieming, Hailu, Eskinder, Boerstler, David
• Granted Patent: US 7,420,400 B2
• Time in Patent Office: Days
• US Class Current: 702/79
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31726 Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922

Abstract

The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

Claims

1. A method of calibrating a duty cycle measurement (DCM) circuit for determining the duty cycle of a digital signal, the method comprising:

supplying the digital signal to the duty cycle measurement (DCM) circuit, the DCM circuit being situated on an integrated circuit (IC) that includes a capacitor;

charging, by charger circuitry in the DCM circuit, the capacitor to a voltage value that depends on the duty cycle of the digital signal;

varying the duty cycle of the digital signal to a plurality of different duty cycle values, the digital signal charging the capacitor to a different voltage value for each of the duty cycle values thereof; and

storing, in a data store, each voltage value and the corresponding duty cycle value.

2. The method of claim 1, wherein the supplying step comprises supplying, by a reference clock circuit, the digital signal to the DCM circuit.

3. The method of claim 1, wherein the charging step comprises charging, by a charge pump in the charger circuitry, the capacitor.

4. The method of claim 1, wherein the digital signal includes a plurality of pulses, each pulse including first and second logic states, the charging circuit charging the capacitor up during the first logic states of the pulses, the charging circuit discharging the capacitor during the second logic state of the pulses, the first and second logic states exhibiting respective durations that define the duty cycle of a particular digital signal, thus leaving a voltage value on the capacitor related to the duty cycle of the plurality of pulses.

5. The method of claim 1, wherein the storing step comprises storing a look-up table in the data store, the look-up table including a plurality of capacitor voltage values and a respective plurality of duty cycle values.

6. The method of claim 5, wherein the plurality of voltage values vary linearly with the respective plurality of duty cycle values.

7. A method of determining the duty cycle of a digital signal, the method comprising:

supplying a first digital signal to a duty cycle measurement (DCM) circuit situated on an integrated circuit (IC) that includes a capacitor;

charging, by charger circuitry in the DCM circuit, the capacitor to a voltage value that depends on the duty cycle of the first digital signal;

varying the duty cycle of the first digital signal to a plurality of different known duty cycle values, the first digital signal charging the capacitor to a different voltage value for each of the known duty cycle values thereof;

storing, in a data store, each voltage value and the corresponding known duty cycle value;

supplying a second digital signal to the DCM circuit, the second digital signal exhibiting an unknown duty cycle;

charging, by the charger circuitry, the capacitor with the second digital signal to a voltage value corresponding to the unknown duty cycle of the second digital signal; and

accessing the data store to determine to which duty cycle the voltage value of the second digital signal corresponds.

8. The method of claim 7, further comprising interpolating the known duty cycle values and corresponding voltage values in the data store to determine the duty cycle to which the voltage value of the second digital signal corresponds.

9. The method of claim 7, further comprising extrapolating from the known duty cycle values and corresponding voltage values in the data store to determine the duty cycle to which the voltage value of the second digital signal corresponds.

10. The method of claim 7, wherein the supplying step comprises supplying, by a reference clock circuit, the first digital signal to the DCM circuit.

11. The method of claim 7, wherein the charging step comprises charging, by a charge pump in the charger circuitry, the capacitor.

12. The method of claim 7, wherein the first digital signal includes a plurality of pulses, each pulse including first and second logic states, the charging circuit charging the capacitor up during the first logic states of the pulses, the charging circuit discharging the capacitor during the second logic state of the pulses, the first and second logic states exhibiting respective durations that define the duty cycle of a particular first digital signal, thus leaving a voltage value on the capacitor related to the duty cycle of the plurality of pulses.

13. The method of claim 7, wherein the storing step comprises storing a look-up table in the data store, the look-up table including a plurality of capacitor voltage values and a respective plurality of duty cycle values.

14. The method of claim 13, wherein the plurality of voltage values vary linearly with the respective plurality of duty cycle values.

15. A duty cycle measurement system that determines the duty cycle of a digital signal, the system comprising:

a duty cycle measurement (DCM) circuit situated on an integrated circuit (IC), the DCM circuit including;

an input that receives a digital signal exhibiting a duty cycle;

a capacitor;

charger circuitry, coupled to the input and the capacitor, that charges the capacitor to a voltage that depends on the duty cycle of the digital signal;

an output, coupled to the capacitor, that provides a voltage value corresponding to the duty cycle of the digital signal;

a reference clock circuit, coupled to the input, that supplies a reference clock signal to the input as the digital signal, the reference clock circuit varying the duty cycle of the reference clock signal to a plurality of different known duty cycle values, the reference clock signal charging the capacitor to a respective voltage value for each of the known duty cycle values thereof; and

a data store, coupled to the output, that stores the respective voltage values and corresponding known duty cycle values.

16. The system of claim 15, further comprising a test clock circuit, coupled to the input, that supplies a test clock signal to the DCM circuit as the digital signal, the test clock signal exhibiting an unknown duty cycle.

17. The system of claim 16, wherein the charger circuitry charges the capacitor with the test clock signal to a voltage value corresponding to the unknown duty cycle of the test clock signal.

18. The system of claim 17, further comprising a control mechanism, coupled to the DCM circuit, that accesses the data store to determine to which duty cycle the voltage value of the test clock signal corresponds.

19. The system of claim 16, wherein the reference clock circuit and the test clock circuit are combined in a common clock circuit.

20. The system of claim 15, wherein the charger circuitry includes a charge pump that charges the capacitor.

21. The system of claim 15, wherein the reference clock signal includes a plurality of pulses, each pulse including first and second logic states, the charging circuit charging the capacitor up during the first logic states of the pulses, the charging circuit discharging the capacitor during the second logic state of the pulses, the first and second logic states exhibiting respective durations that define the duty cycle of a particular reference clock signal, thus leaving a voltage value on the capacitor related to the duty cycle of the plurality of pulses of each particular reference clock signal.

22. The system of claim 15, wherein the data store includes a look-up table that stores a plurality of capacitor voltage values and a respective plurality of duty cycle values.

23. The system of claim 22, wherein the plurality of voltage values vary linearly with the respective plurality of duty cycle values.

24. The system of claim 15, wherein the IC comprises one of a microprocessor and a microcontroller.

25. An information handling system (IHS) that determines the duty cycle of a digital signal, the IHS comprising:

a processor situated on an integrated circuit (IC), the IC including a duty cycle measurement (DCM) circuit;

a memory coupled to the processor;

the DCM circuit including;

an input that receives a digital signal exhibiting a duty cycle;

a capacitor;

charger circuitry, coupled to the input and the capacitor, that charges the capacitor to a voltage that depends on the duty cycle of the digital signal;

an output, coupled to the capacitor, that provides a voltage value corresponding to the duty cycle of the digital clock signal;

a reference clock circuit, coupled to the input, that supplies a reference clock signal to the input as the digital signal, the reference clock circuit varying the duty cycle of the reference clock signal to a plurality of different known duty cycle values, the reference clock signal charging the capacitor to a respective voltage value for each of the known duty cycle values thereof; and

a data store, coupled to the output, that stores the respective voltage values and corresponding known duty cycle values.

26. The IHS of claim 25, further comprising a test clock circuit, coupled to the input, that supplies a test clock signal to the DCM circuit, the test clock signal exhibiting an unknown duty cycle.

27. The IHS of claim 27, wherein the charger circuitry charges the capacitor with the test clock signal to a voltage value corresponding to the unknown duty cycle of the test clock signal.

28. The IHS of claim 27, further comprising a control mechanism, coupled to the DCM circuit, that accesses the data store to determine to which duty cycle the voltage value of the test clock signal corresponds.

29. A computer program product stored on a computer operable medium for controlling the determination of the duty cycle of a digital signal by a duty cycle measurement (DCM) circuit, the computer program product comprising:

storing means for storing voltage values and respective duty cycle values derived from the DCM circuit, wherein the DCM circuit is situated in an integrated circuit that includes a capacitor, a first digital signal exhibiting a duty cycle being supplied to the DCM circuit, the DCM circuit including means for charging the capacitor to a voltage value that depends on the duty cycle of the first digital signal;

means for varying the duty cycle of the first digital signal to a plurality of different known duty cycle values, the first digital signal charging the capacitor to a different voltage value for each of the known duty cycle values thereof;

wherein the means for storing stores each such voltage value and the corresponding known duty cycle value, wherein a second digital signal exhibiting an unknown duty cycle is supplied to the DCM circuit and the means for charging charges the capacitor with the second digital signal to a new voltage value corresponding to the unknown duty cycle of the second digital signal; and

means for accessing the storing means to determine to which duty cycle the voltage value of the second digital signal corresponds.

30. The computer program product of claim 29, wherein the means for storing comprises a look-up table.

31. The computer program product of claim 29, further comprising means for interpolating from the voltage values and respective duty cycle values in the storing means to determine the duty cycle corresponding to the new voltage value.

32. The computer program product of claim 29, further comprising means for extrapolating from the voltage values and respective duty cycle values in the storing means to determine the duty cycle corresponding to the new voltage value.