Programmable logic device including programmable interface core and central processing unit
First Claim
1. A programmable logic device comprising:
- a central processing unit (CPU);
on-chip peripheral bus;
a programmable interface coupled between the CPU an the on-chip peripheral bus, wherein the programmable interface includes a core designated by a user, the programmable interface comprising an address decoder for accessing devices coupled to the on-chip peripheral bus; and
a first device coupled to the on-chip peripheral bus for one of providing information to and receiving information from the CPU via the programmable interface using an address decoded by the address decoder of the programmable interface.
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Abstract
A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD provides significant flexibility in providing features that can be parameterized based on the user'"'"'s needs and/or associated design. Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD. Finally, the functions of the processor local bus can be efficiently limited, thereby allowing the PLD to approach the performance level of an ASIC.
119 Citations
19 Claims
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1. A programmable logic device comprising:
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a central processing unit (CPU);
on-chip peripheral bus;
a programmable interface coupled between the CPU an the on-chip peripheral bus, wherein the programmable interface includes a core designated by a user, the programmable interface comprising an address decoder for accessing devices coupled to the on-chip peripheral bus; and
a first device coupled to the on-chip peripheral bus for one of providing information to and receiving information from the CPU via the programmable interface using an address decoded by the address decoder of the programmable interface. - View Dependent Claims (2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14)
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7. (canceled)
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15. A software tool for configuring a programmable logic device having an embedded microprocessor, the software tool including:
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a user-designated core for selectively providing connectivity between a plurality of masters on the programmable logic device and a plurality of slaves on the programmable logic device by way an on-chip peripheral bus, wherein the microprocessor is one such master and wherein the user-designated core comprises an address decoder for accessing devices coupled to the on-chip peripheral bus; and
a configuration bitstream generated by the software tool to configure the programmable logic device to enable the address decoder of the programmable interface core. - View Dependent Claims (16, 17, 18, 19)
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Specification