PREDICTIVE, ADAPTIVE POWER SUPPLY FOR AN INTEGRATED CIRCUIT UNDER TEST

• US 20070257696A1
• Filed: 07/17/2007
• Published: 11/08/2007
• Est. Priority Date: 01/18/2000
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles, Eldridge, Benjamin
• Granted Patent: US 7,714,603 B2
• Time in Patent Office: Days
• US Class Current: 324/762.10
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT'"'"'s demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT'"'"'s power input terminal.

Claims

1. An apparatus for supplying current to a semiconductor device during a test of the semiconductor device by an integrated circuit tester accessing input/output (I/O) terminals of the semiconductor device via interface means providing signal paths between the I/O terminals and the integrated circuit tester, wherein the semiconductor device includes a power input terminal for receiving supply current via a power conductor provided by the interface means, and wherein the semiconductor device temporarily increases its demand for supply current following each of a set of edges of a clock signal applied as input to the semiconductor device, the apparatus comprising:

first means for supplying a first current to the power input terminal during the test;

second means for supplying a current pulse to the power input terminal following each of the edges of the clock signal supplementing the first current, wherein a magnitude of the current pulse is a function of magnitudes represented by a prediction signal and an adaption signal; and

third means for adjusting the magnitude represented by the adaption signal in response to a voltage appearing at the power input terminal,

wherein the magnitude represented by the prediction signal is set proportional to a predicted amount by which the semiconductor device will increase its demand for current at its power input terminal following a next one of the clock signal edges.

2-24. -24. (canceled)