ANALOG TO DIGITAL CONVERTER CIRCUIT WITH OFFSET REDUCTION AND IMAGE SENSOR USING THE SAME
First Claim
1. A circuit, comprising:
- a comparator comprising a plurality of input nodes;
said comparator configured to perform an offset reduction operation to compensate for offset between the plurality of input nodes; and
said comparator configured to perform a decision operation using positive feedback to decide which of the plurality of input nodes is being provided with a highest input voltage.
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Abstract
An image sensor may be improved by using ADCs that compensate for the effect of comparator input offset on comparator decisions. Offset compensation may be implemented in an ADC by using an amplifier section between the input of the ADC and a comparator section of the ADC to amplify the signals supplied to the comparator inputs and thereby reduce the effect of comparator offset on the comparator decision. The comparator section may be an autozeroing comparator section that is capable of performing an offset reduction operation to store offset compensation values at capacitors provided at its inputs. The amplifier section may be an autozeroing amplifier section having one or more amplifier stages that are capable of performing an offset reduction operation to store offset compensation values at capacitors provided at their inputs. Offset compensation may also be implemented using an autozeroing comparator section without a preceding amplifier section. Related methods of operation cause the circuits to perform the offset reduction operations.
29 Citations
20 Claims
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1. A circuit, comprising:
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a comparator comprising a plurality of input nodes;
said comparator configured to perform an offset reduction operation to compensate for offset between the plurality of input nodes; and
said comparator configured to perform a decision operation using positive feedback to decide which of the plurality of input nodes is being provided with a highest input voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method, comprising:
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performing, by a comparator having a plurality of input nodes, an offset reduction operation to compensate for offset between the plurality of input nodes; and
performing, by the comparator, a decision operation using positive feedback to decide which of the plurality of input nodes is being provided with a highest input voltage. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A circuit, comprising:
comparator means for performing an offset reduction operation to compensate for offset between a plurality of input nodes of the comparator means, and for performing a decision operation using positive feedback to decide which of the plurality of input nodes is being provided with a highest input voltage. - View Dependent Claims (17, 18, 19, 20)
Specification