High frequency divider with input-sensitivity compensation

• US 20070257735A1
• Filed: 05/03/2006
• Published: 11/08/2007
• Est. Priority Date: 05/03/2006
• Status: Abandoned Application

• Current Assignee: National Central University
• Original Assignee: National Central University
• Inventors: Chan, Yi-Jen, Huang, Fan-Hsiu
• Application Number:
  US11/416,224
• Publication Number:
  US 20070257735A1
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: H03B 19/14 by means of a semiconductor device
• CPC Class Codes: H03K 27/00 Pulse counters in which pulses are continuously circulated in a closed loop; Analogous frequency dividers feedback shift register counters H03K23/54
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

A frequency divider, which has a cross-coupled inductor-capacitor (LC) structure or a ring structure, is inputted with a direct current (DC) control voltage from an input terminal. By doing so, the frequency divider can adjust an oscillation frequency; and further compensate the input power sensitivity, lower the power consumption and increase the division range. The frequency divider can be used in high-band/high-speed digital or analog communication systems.

Claims

1. A high frequency divider with input-sensitivity compensation comprising components of:

an input terminal;

an injection transistor;

a first inductance;

a second inductance;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a first output buffer;

a second output buffer;

a first output terminal;

a second output terminal;

a voltage controller,

wherein said components are connected electrically to obtain a cross-coupled inductor-capacitor (LC) structure.

2. The frequency divider according to claim 1,

where in said frequency divider is an oscillator;

and

wherein a direct-current (DC) control voltage is inputted into said voltage control terminal to obtain an oscillation frequency from said frequency divider.

3. The frequency divider according to claim 2,

wherein said oscillation frequency is ad adjusted under different levels by controlling a voltage value of said DC control voltage.

4. The frequency divider according to claim 2,

wherein said oscillation frequency is a reciprocal of an even times of a frequency of an input signal.

5. The frequency divider according to claim 4,

wherein said input signal is a sine wave.

6. The frequency divider according to claim 4,

wherein said input signal has a frequency deviated from said oscillation frequency;

and

wherein a DC control voltage is inputted into a voltage control terminal to adjust said oscillation frequency into said reciprocal of said even times of said frequency of said input signal when said input signal has a frequency being deviated from said oscillation frequency.

7. The frequency divider according to claim 1,

wherein said third transistor is selected from a group consisting of a varactor and a diode.

8. The frequency divider according to claim 1,

wherein said fourth transistor is selected from a group consisting of a varactor and a diode.

9. The frequency divider according to claim 1,

wherein said injection transistor, said first transistor, said second transistor, said third transistor, said fourth transistor are each selected from a group consisting of a metal oxide semiconductor (MOS) transistor, high electron mobility transistor (HEMT), a bipolar junction transistor (BJT) and a Heterojunction Bipolar Transistor (HBT).

10. The frequency divider according to claim 1,

wherein said first inductance has a shape selected from a group consisting of a spiral shape and a curved shape.

11. The frequency divider according to claim 1,

wherein said second inductance has a shape selected from a group consisting of a spiral shape and a curved shape.

12. The frequency divider according to claim 1,

wherein said output buffer has a structure selected from a group consisting of an emitter-coupled logic (ECL), a common mode logic (CML), a positive-ECL (PECL) and a low voltage differential signaling (LVDS) circuit.

13. The frequency divider according to claim 1,

wherein said frequency divider outputs a divisor of an even number.

14. A high frequency divider with input-sensitivity compensation, comprising components of:

a plurality of inverters

an input terminal;

an injection transistor;

an output buffer; and

an output terminal,

wherein said plurality of inverters are connected serially; and

wherein said components are connected electrically to obtain a ring structure.

15. The frequency divider according to claim 14,

wherein said plurality of inverters has an odd number of inverters.

16. The frequency divider according to claim 14,

wherein each inverter in said plurality of inverters comprises a fifth transistor, a sixth transistor and a seventh transistor;

and

wherein said fifth transistor, said sixth transistor and said seventh transistor are connected electrically.

17. The frequency divider according to claim 16,

wherein said seventh transistor is a delay-time adjusting transistor.

18. The frequency divider according to claim 14,

wherein said voltage control terminal receives an in put of a DC control voltage to adjust a Resistor-Capacitor (RC) time of each inverter to adjust an oscillation frequency.