FABRICATION OF VERTICAL SIDEWALLS ON (110) SILICON SUBSTRATES FOR USE IN SI/SIGE PHOTODETECTORS

• US 20070259467A1
• Filed: 05/02/2006
• Published: 11/08/2007
• Est. Priority Date: 05/02/2006
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Maa, Jer-Shen, Lee, Jong-Jan, Hsu, Sheng, Tweet, Douglas
• Granted Patent: US 7,297,564 B1
• Time in Patent Office: Days
• US Class Current: 438/48
• CPC Class Codes: H01L 31/1812 including only AIVBIV alloys, e.g. SiGe
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors includes preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface. Masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane and etching the silicon (110) layer to remove an un-masked portion thereof, leaving a patterned silicon (110) layer having vertical silicon (111) sidewalls. Removing the mask; growing SiGe-containing layers on the patterned silicon (110) layer; and fabricating a photodetector.

Claims

1. A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors, comprising:

preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface;

masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane;

etching the silicon (110) layer to remove an un-masked portion thereof, leaving a patterned silicon (110) layer;

removing the mask;

growing SiGe-containing layers on the patterned silicon (110) layer; and

fabricating a photodetector.

2. The method of claim 1 wherein said preparing a silicon (110) layer includes preparing a bulk silicon (110) substrate.

3. The method of claim 1 wherein said preparing a silicon (110) layer includes preparing a SOI wafer having a silicon (110) top silicon layer thereon.

4. The method of claim 1 wherein said masking the silicon (110) layer includes masking and patterning the silicon (110) layer with a masking taken from the group of maskings consisting of photoresist and hardmasks.

5. The method of claim 1 wherein said etching the silicon (110) layer includes etching by a selective wet etch process.

6. The method of claim 1 wherein said etching the silicon (110) layer includes etching by a RIE process and then further etching the silicon (110) layer by a selective wet etch process which etches silicon (110) planes faster than silicon (111) planes, leaving a patterned silicon (110) surface having silicon (111) sidewalls.

7. A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors, comprising:

preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface, wherein said preparing a silicon (110) layer includes preparing a bulk silicon (110) substrate or preparing a SOI wafer having a silicon (110) top silicon layer thereon;

masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane;

etching the silicon (110) layer to remove an un-masked portion thereof, leaving a patterned silicon (110) layer;

removing the mask;

growing SiGe-containing layers on the patterned silicon (110) layer; and

fabricating a photodetector.

8. The method of claim 7 wherein said masking the silicon (110) layer includes masking and patterning the silicon (110) layer with a masking taken from the group of maskings consisting of photoresist and hardmasks.

9. The method of claim 7 wherein said etching the silicon (110) layer includes etching by a selective wet etch process.

10. The method of claim 7 wherein said etching the silicon (110) layer includes etching by a RIE process and then further etching the silicon (110) layer by a selective wet etch process which etches silicon (110) planes faster than silicon (111) planes, leaving a patterned silicon (110) surface having vertical silicon (111) sidewalls.

11. A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors, comprising:

preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface;

masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane;

etching the silicon (110) layer to remove an un-masked portion thereof, leaving a patterned silicon (110) layer, wherein said etching the silicon (110) layer includes etching by a RIE process and then further etching the silicon (110) layer by a selective wet etch process which etches silicon (110) planes faster than silicon (111) planes, leaving a patterned silicon (110) surface having vertical silicon (111) sidewalls.;

removing the mask;

growing SiGe-containing layers on the patterned silicon (110) layer; and

fabricating a photodetector.

12. The method of claim 11 wherein said preparing a silicon (110) layer includes preparing a bulk silicon (110) substrate.

13. The method of claim 11 wherein said preparing a silicon (110) layer includes preparing a SOI wafer having a silicon (110) top silicon layer thereon.

14. The method of claim 11 wherein said masking the silicon (110) layer includes masking and patterning the silicon (110) layer with a masking taken from the group of maskings consisting of photoresist and hardmasks.

15. The method of claim 11 wherein said etching the silicon (110) layer includes etching by a selective wet etch process.