Method for Providing Mixed Stacked Structures, with Various Insulating Zones and/or Electrically Conductiong Zones Vertically Localized

• US 20070259528A1
• Filed: 10/06/2005
• Published: 11/08/2007
• Est. Priority Date: 10/06/2004
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Moriceau, Hubert, Morales, Christophe, Dechamp, Jerome, Zussy, Marc
• Granted Patent: US 7,541,263 B2
• Time in Patent Office: Days
• US Class Current: 438/702
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76259 with separation/delamination along a porous layer

Abstract

The invention relates to a method for producing a semiconducting structure on a semiconducting substrate, one surface of which has a topology, this method including:

• • a) a step for forming a first layer (24) in a first insulating material on said surface,
  • b) a step for forming a second layer in a second insulating material (28), less dense than the first insulating material, with a thickness between 2.5 p and 3.5 p, c) a step for planarization of the assembly.

Claims

1-37. -37. (canceled)

38. A method for producing a semiconducting structure, on a semiconducting substrate having a surface topology, this method including:

a) a step for forming a first layer in a first insulating material on said surface,

b) a step for forming a second layer on the first layer, in a second insulating material, less dense than the first insulating material,

c) a step for thinning the assembly.

39. The method according to claim 38, the topology being formed by patterns etched in the substrate, separated by trenches.

40. The method according to claim 39, the etched patterns having a depth between 1 nm and 10 μ

m.

41. The method according to claim 39, the etched patterns having a width between 1 μ

m and 5 mm.

42. The method according to claim 38, the substrate being a composite substrate.

43. The method according to claim 42, including a surface insulating film.

44. The method according to claim 38, the first insulator layer being a layer in accordance with the topology of the substrate.

45. The method according to claim 38, step c) leaving a layer of first insulator on the surface.

46. The method according to claim 45, further including an additional thinning step, leaving an alternation of semiconducting areas and of insulating areas on the surface.

47. The method according to claim 38, the thinning step being preceded with a step for densifying the second insulating material.

48. The method according to claim 38, the first insulating material being thermal oxide SiO₂.

49. The method according to claim 38, the second insulating material being deposited oxide SiO₂.

50. The method according to claim 49, the oxide being deposited by plasma vapor phase deposition.

51. The method according to claim 38, the insulating material being in Al₂O₃, or AlN, or SiON, or Si₃N₄, or diamond, or HfO₂, or in a dielectric material with a high dielectric constant.

52. The method according to claim 38, the semiconducting material being in silicon or in Si_1-xGe_x (0<

x<

1).

53. The method according to claim 38, further including an assembly step with a second substrate.

54. The method according to claim 53, the assembly being achieved by molecular adhesion.

55. The method according to claim 53, the second substrate being in a second semiconducting material.

56. The method according to claim 55, the second substrate further including an insulator layer on the second semiconducting material.

57. The method according to claim 53, an insulating film being formed on at least one of the two substrates.

58. The method according to claim 53, the first substrate having at least one area of a first type of conductivity, and the second substrate having at least one area of the opposite conductivity type.

59. The method according to claim 53, further including a step for thinning the first and/or the second substrate.

60. The method according to claim 59, the step for thinning either one or both of the substrates being performed by forming an embrittlement layer or area.

61. The method according to claim 60, the embrittlement layer or area being produced by a layer of porous silicon.

62. The method according to claim 60, the formation of an embrittlement layer or area being produced by ion implantation in the first or second substrate.

63. The method according to claim 62, the implanted ions being hydrogen ions or a mixture of hydrogen ions and helium ions.

64. The method according to claim 59, the thinning step being achieved by polishing or etching.

65. The method according to claim 38, the first substrate including areas with different dopings.

66. A method for producing a semiconducting structure, comprising the formation:

a1) of a first insulating area in a semiconducting substrate,

b1) and then the formation of at least a second insulating area in the same substrate,

steps a1) and b1) being carried out according to claim 38.

67. The method according to claim 66, steps a1) and b1) being carried out with different masks.

68. The method according to claim 66, at least two of the formed insulating areas having different depths and/or widths in the substrate and/or being for formed with different insulating materials.

69. A method for producing a semiconducting structure, on a semiconducting substrate having pads in a first insulating material protruding from the surface of the substrate, this method including:

a) a step for forming a second layer, on the substrate and the pads, in a second insulating material, less dense than the first insulating material,

b) a step for thinning the assembly.

70. The method according to claim 69, the pads being formed in the etched areas of the semiconducting area.

71. The method according to claim 69, the pads being formed by thermal oxidation of the semiconducting substrate, or the pads being for formed by LPCVD and the second insulating material layer in PECVD.

72. The method according to claim 69, step b) leaving a second insulating material layer at the surface or leaving at the surface an alternation of second insulating material areas and of first insulating material areas.

73. The method according to claim 69, the thinning step being preceded with a step for densifying the second insulating material.

74. The method according to claim 69, the first insulating material being thermal oxide SiO₂.

75. The method according to claim 69, the second insulating material being deposited oxide SiO₂.

76. The method according to claim 75, the oxide being deposited by plasma vapor phase deposition.

77. The method according to claim 69, the insulating material being in Al₂O₃, or AlN, or SiON, or Si₃N₄, or diamond, or HfO₂, or in a dielectric material with a high dielectric constant.

78. The method according to claim 69, the semiconducting material being in silicon or in Si_1-xGe_x (0<

x<

1).

82. The method according to claim 69, further including an assembly step with a second substrate.

83. The method according to claim 82, the assembly being achieved by molecular adhesion.

84. The method according to claim 82, the second substrate being in a second semiconducting material.

85. The method according to claim 84, the second substrate further including an insulator layer on the second semiconducting material.

86. The method according to claims 82, an insulating film being formed on at least one of the two substrates.

87. The method according to claim 82, the first substrate having at least one area of a first type of conductivity, and the second substrate having at least one area of the opposite conductivity type.

88. The method according to claim 82, further including a step for thinning the first and/or the second substrate.

89. The method according to claim 88, the step for thinning either one or both of the substrates being performed by for forming an embrittlement layer or area.

90. The method according to claim 89, the embrittlement layer or area being produced by a layer of porous silicon.

91. The method according to claim 89, the formation of an embrittlement layer or area being produced by ion implantation in the first or second substrate.

92. The method according to claim 91, the implanted ions being hydrogen ions or a mixture of hydrogen ions and helium ions.

93. The method according to claim 88, the thinning step being achieved by polishing or etching.

94. The method according to claim 69, the first substrate including areas with different dopings.