DRAM remote access cache in local memory in a distributed shared memory system

• US 20070260821A1
• Filed: 05/04/2006
• Published: 11/08/2007
• Est. Priority Date: 05/04/2006
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Landin, Anders, Hagersten, Erik, Zeffer, Hakan
• Granted Patent: US 7,509,460 B2
• Time in Patent Office: Days
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a remote address or a local address. A first portion of the memory in the node is allocated to store copies of remote data and a remaining portion stores local data. The control unit is configured to write writeback data to a location in the first portion. The writeback data corresponds to a writeback request from the intranode interconnect that has an associated remote address detected by the logic. The control unit is configured to determine the location responsive to the associated remote address and one or more indicators that identify the first portion in the memory.

Claims

1. A memory controller for a node in a multi-node computer system, the memory controller comprising:

logic configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a remote address mapped to remote memory in another node of the multi-node computer system or a local address mapped to a memory in the node that includes the memory controller, wherein a first portion of the memory in the node is allocated to store copies of remote data and a remaining portion stores local data; and

a control unit coupled to the logic, wherein the control unit is configured to write writeback data to a location in the first portion, wherein the writeback data corresponds to a writeback request from the intranode interconnect that has an associated remote address detected by the logic, wherein the control unit is configured to determine the location responsive to the associated remote address and one or more indicators that identify the first portion in the memory, and wherein the writeback request is generated by a cache in the node in response to evicting the writeback data from the cache.

2. The memory controller as recited in claim 1 wherein the one or more indicators comprise a base address of the first portion and a size of the first portion.

3. The memory controller as recited in claim 2 wherein the base address and size are programmable in one or more registers coupled to the control unit.

4. The memory controller as recited in claim 3 further comprising one or more additional registers coupled to the logic, wherein the one or more additional registers are programmable to distinguish remote addresses from local addresses.

5. The memory controller as recited in claim 4 wherein the one or more additional registers store a mask, and wherein the logic is configured to use the mask to mask off one or more portions of an address that do not distinguish remote addresses from local addresses.

6. The memory controller as recited in claim 5 wherein the one or more additional registers further store a match value, wherein the logic is configured to compare the match value to the masked address.

7. The memory controller as recited in claim 6 wherein a mismatch between the match value and the masked address indicates a remote address.

8. The memory controller as recited in claim 1 wherein, if the logic detects a local address for a request, the control unit is configured to read or write the memory identified by the local address according to the type of request.

9. A node comprising:

an intranode interconnect;

a cache coupled to the intranode interconnect, wherein the cache is configured to evict a remote cache line of data and to generate a writeback request on the intranode interconnect, the writeback request comprising the remote cache line and a remote address identifying the remote cache line;

an interface circuit coupled to the intranode interconnect and configured to couple the node to at least one other node via an internode interconnect, the remote address mapped to a remote memory in the at least one other node; and

a memory controller coupled to the intranode interconnect and configured to couple to a memory, wherein the memory controller is configured, responsive to the writeback request and the remote address, to write the remote cache line to a first portion of the memory in the node that is allocated to store copies of remote data, wherein a remaining portion of the memory stores local data, and wherein a location in the first portion, to which the remote cache line is written, is determined responsive to the remote address and one or more indicators that identify the first portion in the memory.

10. The node as recited in claim 9 wherein the one or more indicators comprise a base address of the first portion and a size of the first portion.

11. The node as recited in claim 10 wherein the base address and size are programmable in one or more registers in the memory controller.

12. The node as recited in claim 11 further comprising one or more additional registers in the memory controller, wherein the one or more additional registers are programmable to distinguish remote addresses from local addresses.

13. The node as recited in claim 12 wherein the one or more additional registers store a mask, and wherein the memory controller is configured to use the mask to mask off one or more portions of an address that do not distinguish remote addresses from local addresses.

14. The node as recited in claim 13 wherein the one or more additional registers further store a match value, wherein the memory controller is configured to compare the match value to the masked address.

15. The node as recited in claim 14 wherein a mismatch between the match value and the masked address indicates a remote address.

16. The node as recited in claim 9 wherein, if the memory controller detects a local address for a request, the memory controller is configured to read or write the memory identified by the local address according to the type of request.

17. A method comprising:

evicting a cache line from a cache in a node;

determining that the cache line is remote to the node; and

writing the cache line to a first portion of a memory in the node responsive to the determining, wherein the first portion of the memory is allocated to store copies of remote cache lines, wherein the writing comprises determining a location within the first portion responsive to an address of the cache line and one or more indicators identifying the first portion in the memory.

18. The method as recited in claim 17 wherein the one or more indicators comprise a base address of the first portion and a size of the first portion.

19. The method as recited in claim 17 further comprising:

masking off one or more portions of an address that do not distinguish remote addresses from local addresses; and

comparing a match value to the masked address, wherein a mismatch between the match value and the masked address indicates a remote address.

20. The method as recited in claim 17 further comprising:

detecting a local address for a request; and

reading or writing the memory identified by the local address according to the type of request.