MEMORY MODULE WITH REDUCED ACCESS GRANULARITY

• US 20070260841A1
• Filed: 05/02/2006
• Published: 11/08/2007
• Est. Priority Date: 05/02/2006
• Status: Abandoned Application

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick, Hampel, Craig
• Application Number:
  US11/381,349
• Publication Number:
  US 20070260841A1
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09227 Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Claims

1. A memory module comprising:

a substrate having signal lines thereon that form a control path and first and second data paths; and

first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths, the first and second memory devices having control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

2. The memory module of claim 1 wherein the first memory access command includes a first address value that indicates a storage location to be accessed within the first memory device, and the second memory access command includes a second address value that indicates a storage location to be accessed within the second memory device.

3. The memory module of claim 1 further comprising:

one or more memory devices that, together with the first memory device, constitute a first set of memory devices, each of the memory devices of the first set being coupled to respective signal lines of the first data path and coupled in common to the control path; and

one or more memory devices that, together with the second memory device, constitute a second set of memory devices, each of the memory devices of the second set being coupled to respective signal lines of the second data path and coupled in common to the control path.

4. The memory module of claim 1 wherein the control circuitry within the first and second memory devices to effect concurrent data transfer on the first and second data paths comprises transmit circuitry within the first memory device to transmit read data on the first data path during a first interval and transmit circuitry within the second memory device to transmit read data on the second data path during a second interval, the first and second intervals at least partly overlapping in time.

5. The memory module of claim 1 wherein the control circuitry within the first and second memory devices to effect concurrent data transfer on the first and second data paths comprises receive circuitry within the first memory device to receive write data via the first data path during a first interval and receive circuitry within the second memory device to receive write data via the second data path during a second interval, the first and second intervals at least partly overlapping in time.

6. The memory module of claim 1 wherein the control circuitry within the first and second memory devices to effect concurrent data transfer on the first and second data paths comprises transmit circuitry within the first memory device to transmit read data on the first data path during a first interval and receive circuitry within the second memory device to receive write data via the second data path during a second interval, the first and second intervals at least partly overlapping in time.

7. The memory module of claim 1 further comprising first and second chip-select lines coupled respectively to the first and second memory devices to enable the first and second memory devices to be independently selected.

8. The memory module of claim 7 wherein the first memory device includes sampling circuitry to sample the first memory access command in response to a first chip-select signal received via the first chip-select line, and the second memory device includes sampling circuitry to sample the second memory access command in response to a second chip-select signal received via the second chip-select line.

9. The memory module of claim 1 further comprising a chip-select line coupled in common to the first and second memory devices, and wherein the first memory device includes sampling circuitry to sample signals present on the control path at a first time relative to assertion of a chip-select signal on the chip-select line to receive the first memory access command, and wherein the second memory device includes sampling circuitry to sample signals present on the control path at a second time relative to assertion of the chip-select signal to receive the second memory access command.

10. The memory module of claim 9 wherein the sampling circuitry within each of the first and second memory devices includes a storage register to store a respective sample-latency value that indicates a number of cycles of a clock signal that are to transpire between assertion of the chip-select signal and sampling of signals on the control path.

11. The memory module of claim 10 wherein each of the first and second memory devices includes control circuitry to receive the respective sample-latency value and an associated register-write command from an external source and to load the sample-latency value into the storage register in response to the register-write command.

12. The memory module of claim 9 wherein each of the first and second memory devices includes first and second chip-select inputs and logic circuitry to assert a sample-enable signal at either the first time or the second time according to whether the chip-select signal is received at the first or second chip-select input, and wherein the chip-select line is coupled to the first chip-select input of the first memory device and to the second chip-select input of the second memory device.

13. The memory module of claim 1 further comprising a chip-select line coupled in common to the first and second memory devices, and wherein the first memory device includes sampling circuitry to sample signals present on the control path in response to a logic-high state of the chip-select line to receive the first memory access command, and wherein the second memory device includes sampling circuitry to sample signals present on the control path in response to a logic-low state of the chip-select line to receive the second memory access command.

14. The memory module of claim 13 wherein the sampling circuitry within each of the first and second memory devices includes a storage register to store a respective level-select value that indicates whether signals on the control path are to be sampled in response to a logic-high or logic-low state of chip-select line.

15. The memory module of claim 14 wherein each of the first and second memory devices includes control circuitry to receive the respective level-select value and an associated register-write command from an external source and to load the sample-latency value into the storage register in response to the register-write command.

16. The memory module of claim 13 wherein each of the first and second memory devices includes first and second chip-select inputs and logic circuitry to assert a sample-enable signal in response to either the logic-high state or the logic-low state of the chip-select line according to whether the chip-select line is coupled to the first or second chip-select input, and wherein the chip-select line is coupled to the first chip-select input of the first memory device and to the second chip-select input of the second memory device.

17. The memory module of claim 1 wherein the first memory device has an identification circuit to enable execution of memory access commands that include a first identifier value and the second memory device has an identification circuit to enable execution of memory access commands that include a second identifier value, and wherein the first and second memory access commands include the first and second identifier values, respectively.

18. The memory module of claim 17 wherein the identification circuit of the first memory device includes a storage register to store the first identifier value in response to a register-write instruction from an external device.

19. The memory module of claim 1 further comprising third and fourth memory devices coupled in common to the control path and coupled respectively to the first and second data paths, the third and fourth memory devices having control circuitry to receive respective third and fourth memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the third and fourth memory access commands during an interval in which the first and second memory devices are disabled from effecting data transfer on the first and second data paths.

20. The memory module of claim 19 wherein the substrate has distinct first and second surfaces and wherein the first and second memory devices are disposed on the first surface and the third and fourth memory devices are disposed on the second surface.

21. The memory module of claim 20 further comprising first and second sets of chip-select lines, each set including one or more constituent chip-select lines, the first set of chip-select lines being coupled to the first and second memory devices and the second set of chip-select lines being coupled to the third and fourth memory devices to enable the first and second memory devices to be selected independently of the third and fourth memory devices.

22. A method of operation within first and second memory devices that are disposed on a memory module and coupled to respective first and second data paths and to a common control path, the method comprising:

receiving, via the control path, a first memory access command within the first memory device and a second memory access command within the second memory device;

conveying first data between the first memory device and the first data path over a first interval and in response to the first memory access command; and

conveying second data between the second memory device and the second data path over a second interval and in response to the second memory access command, the first and second intervals at least partly overlapping in time.

23. The method of claim 22 wherein receiving first and second memory access commands comprises receiving first and second memory read commands, and wherein conveying the first data between the first memory device and the first data path comprises outputting first read data from the first memory device to the first data path in response to the first memory read command, and wherein conveying the second data between the second memory device and the second data path comprises outputting second read data from the second memory device to the second data path in response to the second memory read command.

24. The method of claim 22 wherein receiving first and second memory access commands comprises receiving first and second memory write commands, and wherein conveying the first data between the first memory device and the first data path comprises receiving first write data from the first data path into the first memory device in response to the first memory write command, and wherein conveying the second data between the second memory device and the second data path comprises receiving second write data from the second data path into the second memory device in response to the second memory write command.

25. The method of claim 22 wherein receiving first and second memory access commands comprises receiving a memory read command within the first memory device and a memory write command within the second memory device, and wherein conveying the first data between the first memory device and the first data path comprises outputting read data from the first memory device to the first data path in response to the memory read command, and wherein conveying the second data between the second memory device and the second data path comprises receiving write data from the second data path into the second memory device in response to the memory write command.

26. The method of claim 22 wherein receiving the first memory access command within the first memory device and the second memory access command within the second memory device comprises enabling respective receiver circuits within the first and second memory devices to sample signals present on the control path at respective, non-overlapping intervals.

27. The method of claim 26 wherein enabling respective receiver circuits within the first and second memory devices to sample signals present on the control path at respective, non-overlapping intervals comprises detecting assertion of a first chip-select signal at a first time at an input of the first memory device and detecting assertion of a second chip-select signal at a second time at an input of the second memory device.

28. The method of claim 27 wherein the first and second chip-select signals are conveyed to the first and second memory devices via independent chip-select lines.

29. The method of claim 27 wherein the first and second chip-select signals are conveyed to the first and second memory devices via a common chip-select line, and wherein detecting assertion of the first chip-select signal comprises detecting a logic-high state of the chip-select line and wherein detecting assertion of the second chip-select signal comprises detecting a logic-low state of the chip-select line.

30. The method of claim 29 wherein detecting assertion of the first chip-select signal comprises detecting either a logic-high state of the chip select line or a logic-low state of the chip-select line according to a level-select value stored in a configuration register within the first memory device.

31. The method of claim 26 wherein enabling respective receiver circuits within the first and second memory devices to sample signals present on the control path at respective, non-overlapping intervals comprises enabling a sampling circuit within the first memory device at a first time relative to assertion of a first chip-select signal and enabling a sampling circuit within the second memory device at a second time relative to assertion of the first chip-select signal.

32. The method of claim 31 wherein enabling the sampling circuit within the second memory device comprises enabling the sampling circuit within the second memory device to sample signals present on the control path at time that is delayed, relative to the first time, by a number of clock cycles indicated by a sample-latency value stored in a configuration register within the second memory device.

33. The method of claim 22 wherein receiving the first memory access command within the first memory device and the second memory access command within the second memory device comprises determining whether device identifier values associated with the first and second memory access commands match device identifier values associated with the first and second memory devices.

34. A memory system comprising:

signal lines that form a control path and first and second data paths;

a memory controller coupled to the control path to transmit first and second memory access commands thereon, and coupled to the first and second data paths; and

a memory module having first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths, the first and second memory devices to having control circuitry receive the first and second memory access commands, respectively, via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

35. A method of controlling memory devices disposed on a memory module, the method comprising:

transmitting first and second memory access commands to the first and second memory devices, respectively, via a common control path;

receiving, during a first interval and in response to the first memory access command, data output from the first memory device via a first data path; and

receiving, during a second interval and in response to the second memory access command, data output from the second memory device via a second data path, the second interval at least partly overlapping the first interval in time.