INTEGRATED CIRCUIT HAVING A CONDITIONAL YIELD INSTRUCTION AND METHOD THEREFOR

• US 20070260863A1
• Filed: 05/02/2006
• Published: 11/08/2007
• Est. Priority Date: 05/02/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William, Whisenhunt, Gary
• Granted Patent: US 7,584,344 B2
• Time in Patent Office: Days
• US Class Current: 712/245
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

An integrated circuit (10) has a conditional yield instruction (305) which may be used to conditionally yield execution of a currently active thread based on priority and status of other threads. In one embodiment, an I bit 304 may be used to designate whether the priority selection bits (50) are stored in the instruction itself. If the priority selection bits (50) are not stored in the instruction itself, a portion of the instruction (302) may be used to store a location indicator which indicates where the priority selection bits (50) are located (e.g. register file 22).

Claims

1. A method for operating a processor, comprising:

as part of execution of a thread on the processor, executing a conditional yield instruction, wherein executing the conditional yield instruction comprises;

retrieving a plurality of priority selection bits from a first portion of the conditional yield instruction;

using the plurality of priority selection bits for selecting one of a priority criteria; and

based on the selected priority criteria, determining whether the thread executing on the processor yields at least one resource to another thread.

2. The method of claim 1, wherein executing the conditional yield instruction further comprises decoding the conditional yield instruction and determining from a second portion of the conditional yield instruction whether the plurality of priority selection bits are stored as a third portion of the conditional yield instruction.

3. The method of claim 2 further comprising retrieving from a fourth portion of the conditional yield instruction a location indicator indicating a storage location of the plurality of priority selection bits.

4. The method of claim 3 further comprising retrieving the plurality of selection bits from the storage location indicated by the location indicator.

5. The method of claim 1 further comprising accessing a thread-state information storage to activate a ready-to-run thread referenced in the thread-state information storage, if the thread executing on the processor yields the at least one resource.

6. The method of claim 1, wherein the selected priority criteria comprises whether at least one other thread is ready to run.

7. The method of claim 1, wherein the selected priority criteria comprises whether at least one other thread with a higher priority than a priority of the thread currently executing on the processor is ready to run.

8. The method of claim 1, wherein the selected priority criteria comprises whether at least one other thread with an equal priority to a priority of the thread currently executing on the processor is ready to run.

9. The method of claim 1, wherein the selected priority criteria comprises whether at least one other thread with a lower priority than a priority of the thread currently executing on the processor is ready to run.

10. The method of claim 5, wherein the thread-state information storage comprises at least a thread identifier, a thread priority level, and a thread ready-to-run indicator.

11. A method for operating a processor, comprising:

as part of execution of a thread on the processor, executing an instruction, wherein executing the instruction comprises;

retrieving a first portion of the instruction to determine whether the instruction is a conditional yield instruction;

if the instruction is the conditional yield instruction, then retrieving a plurality of priority selection bits from a second portion of the conditional yield instruction;

using the plurality of priority selection bits for selecting one of a priority criteria; and

based on the selected priority criteria, determining whether the thread executing on the processor yields at least one resource to another thread.

12. The method of claim 11, further comprising decoding the conditional yield instruction and determining from a third portion of the conditional yield instruction whether the plurality of priority selection bits are stored as a fourth portion of the conditional yield instruction.

13. The method of claim 12 further comprising retrieving from a fifth portion of the conditional yield instruction a location indicator indicating a storage location of the plurality of priority selection bits.

14. The method of claim 13 further comprising retrieving the plurality of priority selection bits from the storage location indicated by the location indicator.

15. The method of claim 11 further comprising accessing a thread-state information storage to activate a ready-to-run thread referenced in the thread-state information storage, if the thread executing on the processor yields the at least one resource.

16. The method of claim 11, wherein the selected priority criteria comprises whether at least one other thread is ready to run.

17. The method of claim 11, wherein the selected priority criteria comprises whether at least one other thread with a higher priority than a priority of the thread currently executing on the processor is ready to run.

18. The method of claim 11, wherein the selected priority criteria comprises whether at least one other thread with an equal priority to a priority of the thread currently executing on the processor is ready to run.

19. The method of claim 11, wherein the selected priority criteria comprises whether at least one other thread with a lower priority than a priority of the thread currently executing on the processor is ready to run.

20. A method for operating a processor, comprising:

as part of execution of a thread on the processor, executing an instruction, wherein executing the instruction comprises;

retrieving a first portion of the instruction to determine whether the instruction is a conditional yield instruction;

if the instruction is the conditional yield instruction, then retrieving a plurality of priority selection bits;

using the plurality of priority selection bits for selecting one of a priority criteria; and

based on the selected priority criteria, determining whether the thread executing on the processor yields at least one resource to another thread.

21. A method for operating an integrated circuit having a processor, the method comprising:

representing an instruction of the processor using a plurality of bits;

using a first portion of the plurality of bits to determine that the instruction is a conditional yield instruction;

using a second portion of the instruction to determine where the priority selection bits are located;

if the second portion of the instruction determines that the priority selection bits are located in the instruction itself using a third portion of the instruction to store the priority selection bits;

if the second portion of the instruction determines that the priority selection bits are not located in the instruction itself, using a register to store the priority selection bits;

using the priority selection bits to select a selected priority criteria from a plurality of priority criteria;

comparing a priority of a currently executing thread with a priority of a second thread that is ready to run to produce a comparison result; and

using the selected priority criteria and the comparison result to determine if the currently executing thread should yield to the second thread.