Apparatus and Method for Booting a Computing Device from a NAND Memory Device

• US 20070260869A1
• Filed: 04/30/2007
• Published: 11/08/2007
• Est. Priority Date: 05/01/2006
• Status: Abandoned Application

• Current Assignee: Symbol Technologies, Inc. (Zebra Technologies Corporation)
• Original Assignee: Symbol Technologies, Inc. (Zebra Technologies Corporation)
• Inventors: Geiger, Edward, Dade, Nicolas
• Application Number:
  US11/741,953
• Publication Number:
  US 20070260869A1
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

Apparatus and methods are provided for booting a computing device from a NAND flash memory. One apparatus includes a NAND memory device including a boot sector configured to store boot code and an FPGA including an internal memory in communication with the NAND memory device. The FPGA is configured to access the boot sector and load the boot code into the internal memory. A method for booting a computing device having a processor, an FPGA, and a NAND memory device including at least one sector storing boot code and a sector storing operational code includes the steps of the FPGA holding the processor in reset and accessing the boot sector. The FPGA also fetches the boot code from the boot sector and stores the boot code in its internal memory. Also disclosed are machine-readable mediums providing logic, which when executed by an FPGA, causes the FPGA to perform the method.

Claims

1. A computing device, comprising:

a NAND memory device including a boot sector configured to store boot code; and

a field programmable gate array (FPGA) including an internal memory in communication with the NAND memory device, the FPGA configured to access the boot sector and load the boot code into the internal memory.

2. The computing device of claim 1, further comprising:

a processor in communication with the FPGA and the NAND memory device, wherein the FPGA is further configured to hold the processor in reset while the FPGA is loading the boot code.

3. The computing device of claim 2, wherein the NAND memory device is further configured to store operational code, and wherein the FPGA is further configured to:

release the processor from reset; and

provide access to the boot code in the internal memory to the processor.

4. The computing device of claim 1, wherein the NAND memory device is further configured to store a valid checksum, and wherein the FPGA is further configured to:

calculate a checksum of the boot code; and

determine if the calculated checksum matches the valid checksum.

5. The computing device of claim 1, wherein the FPGA is further configured to reset the NAND memory device prior to the FPGA accessing the boot sector.

6. A method for booting a computing device having a processor, a field programmable gate array (FPGA) including internal memory, and a NAND memory device including a boot sector storing boot code and at least one sector storing operational code, the method comprising the steps of:

accessing, via the FPGA, the boot sector;

holding the processor in reset;

fetching the boot code from the boot sector; and

storing the boot in the internal memory.

7. The method of claim 6, the method further comprising the steps of:

calculating a checksum of the boot code; and

determining if the calculated checksum is valid.

8. The method of claim 7, further comprising the steps of:

releasing the processor from reset; and

providing access to the boot code in the internal memory to the processor.

9. The method of claim 6, further comprising the step of resetting the NAND memory device prior to the FPGA accessing the boot sector.

10. A machine-readable medium that provides logic, which when executed by a field programmable gate array (FPGA) in communication with a processor and a NAND memory device including at least one boot sector storing boot code causes the FPGA to:

access, via the FPGA, the boot sector;

hold the processor in reset;

fetch the boot code from the boot sector; and

store the boot in the internal memory.

11. The machine-readable medium of claim 10, the logic further causing the FPGA to:

calculate a checksum of the boot code; and

determine if the calculated checksum is valid.

12. The machine-readable medium of claim 11, the logic further causing the FPGA to:

release the processor from reset; and

provide access to the boot code in the internal memory to the processor.

13. The machine-readable medium of claim 10, the logic further causing the FPGA to reset the NAND memory device prior to the FPGA accessing the boot sector.