Error detection in physical interfaces for point-to-point communications between integrated circuits
First Claim
1. An apparatus for detecting errors in a physical interface that facilitates data communications between integrated circuits (“
- ICs”
), the apparatus comprising;
a decoder configured to decode a subset of encoded data bits to yield decoded data bits; and
a physical interface (“
PI”
) error detection bit extractor configured to extract a physical interface error detection bit from said decoded data bits, said physical interface error detection bit being used to determine whether said encoded data bits include at least one erroneous data bit as an error.
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Accused Products
Abstract
An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface (“PI”) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits. As such, the apparatus uses the physical interface error detection bit to determine whether the encoded data bits include at least one erroneous data bit as an error. In some embodiments, the apparatus includes an error detector configured to operate within a physical layer. In at least one embodiment, the apparatus efficiently transmits error detection codes within, for example, an NB/(N+1)B line coder.
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Citations
38 Claims
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1. An apparatus for detecting errors in a physical interface that facilitates data communications between integrated circuits (“
- ICs”
), the apparatus comprising;
a decoder configured to decode a subset of encoded data bits to yield decoded data bits; and
a physical interface (“
PI”
) error detection bit extractor configured to extract a physical interface error detection bit from said decoded data bits, said physical interface error detection bit being used to determine whether said encoded data bits include at least one erroneous data bit as an error. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
- ICs”
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14. An apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“
- ICs”
), the apparatus comprising;
an N bit-to-N+2 (“
N bit/N+2”
) bit physical layer (“
PHY”
) encoder configured to;
insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and encode said N+1 unencoded data bits to yield N+2 encoded data bits; and
an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit, wherein N represents any integer number of data bits. - View Dependent Claims (15, 16, 17, 18)
- ICs”
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19. A physical interface formed as an integrated circuit (“
- IC”
) on a first substrate portion to detect transmission errors in data exchanged with another IC formed on a second substrate portion, the physical interface comprising;
a plurality of input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to said another IC; and
one or more error recovery modules coupled between said plurality of input ports and output ports, wherein a first error recovery module of said one or more error recovery modules is coupled between at least one of said first subset of input ports and at least one of said first subset of output ports. - View Dependent Claims (20, 21, 22, 23, 24, 25)
- IC”
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26. A method for decoding data bits to at least detect errors at a physical interface, the method comprising:
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decoding a subset of an encoded bit stream having an embedded asynchronous clock to yield decoded data bits;
extracting a physical interface error detection bit from said decoded data bits;
determining said encoded bit stream includes an incorrect bit based on at least said physical interface error detection bit; and
correcting said error at said physical interface. - View Dependent Claims (27, 28, 29, 30)
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31. A high-speed serial communications link between at least two integrated circuits (“
- ICs”
) comprising;
a physical medium for conveying communications data;
a transmitter device coupled to a first end of said physical medium, said transmitter device includes an N bit/N+2 bit encoder that generates encoded data bits with physical interface error detection bits encoded therein; and
a receiver device coupled to a second end of said physical medium, said receiver device includes;
an N+2 bit/N bit decoder that decodes said encoded data bits, and an error detector configured to determine an error using said physical interface error detection bits. - View Dependent Claims (32, 33, 34, 35, 36)
- ICs”
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37. A physical interface for detecting transmission errors at a physical layer during point-to-point communications via parallel data link, the physical interface comprising:
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a parallel port for receiving parallel communications data via said parallel data link, a subset of said parallel communications data including a physical interface error detection bit;
an external clock input configured to receive an external clock to synchronize the reception of said parallel communications data; and
a physical interface error detector configured to use said physical interface error detection bit to determine whether said parallel communications data includes an incorrect bit as an error; and
an error corrector configured to correct said error at said physical interface. - View Dependent Claims (38)
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Specification