Low temperature fabrication of discrete silicon-containing substrates and devices

• US 20070262363A1
• Filed: 04/19/2007
• Published: 11/15/2007
• Est. Priority Date: 02/28/2003
• Status: Abandoned Application

• Current Assignee: Board of Regents of the University of Texas System (University of Texas System)
• Original Assignee: Board of Regents of the University of Texas System (University of Texas System)
• Inventors: Tao, Meng, Shi, Fang
• Application Number:
  US11/788,227
• Publication Number:
  US 20070262363A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

Fabrication methods and processes are described, the methods and processes occurring at a low-temperature and involving passivation. The methods and processes easily incorporate annealing, deposition, patterning, lithography, etching, oxidation, epitaxy and chemical mechanical polishing for forming suitable devices, such as diodes and MOSFETs. Such fabrication is a suitable and more cost-effective alternative to a process of diffusion or doping, typical for forming p-n junctions. The process flow does not require temperatures above 700 degrees Centigrade. Formation of p-n junctions in discrete silicon diodes and MOSFETs are also provided, fabricated at low temperatures in the absence of diffusion or doping.

Claims

1. A method for forming one or more p-n junctions on a silicon-containing substrate comprising:

providing onto a surface of the substrate at least one atomic layer of a passivating agent to form a passivated surface, wherein the substrate is a semiconductor material of one conduction type;

depositing a metal on the passivated surface and forming a p-n junction, wherein a region of the passivated surface becomes a semiconductor material of another type.

2. The method of claim 1, wherein the passivating agent minimizes electronic states bound to the surface.

3. The method of claim 1, wherein the passivating agent is provided at one atomic layer.

4. The method of claim 1, wherein the substrate is selected from the group consisting of silicon, germanium, silicon-germanium, silicon-carbide, derivations and combinations thereof.

5. The method of claim 1, wherein the substrate is n-type, the metal has a large work function and at least a portion of the passivated surface is modified to p-type.

6. The method of claim 1, wherein the substrate is p-type, the metal has a small work function and at least a portion of the passivated surface is modified to n-type.

7. The method of claim 1, wherein the passivating agent is selected from the group consisting of a Group V, VI, or VII cogener, or hydrogen.

8. The method of claim 1, wherein the passivating agent is selected from the group consisting of sulfur, selenium, and tellurium.

9. The method of claim 1, wherein the method occurs at a temperature below 700 degrees Centigrade.

10. The method of claim 1, wherein the method further comprises a step of one or more of the group consisting of annealing, deposition, patterning, lithography, etching, oxidation, epitaxy and chemical mechanical polishing.

11. The method of claim 1, wherein the method is a process flow for making a discrete silicon device.

12. The method of claim 11, wherein the device is a diode.

13. The method of claim 11, wherein the device is a MOSFET.

14. The method of claim 1, wherein the method further comprises forming a source, gate and drain in a MOSFET.

15. The method of claim 1, wherein the region is under the deposited metal.

16. A method of forming one or more p-n junctions on a silicon-containing substrate by providing one or more n-type regions on a surface of a p-type silicon-containing substrate after providing a low work-function metal.

17. A method of forming one or more p-n junctions on a silicon-containing substrate by providing one or more p-type regions on a surface of a n-type silicon-containing substrate after providing a high work-function metal.

18. A method for forming one or more p-n junctions on a silicon-containing substrate comprising:

providing at least one atomic layer of a passivating agent onto a surface of a substrate, wherein the substrate is a semiconductor material of one conduction type;

applying a metal layer on the passivated surface to form a p-n junction, wherein a region of the passivated surface becomes a semiconductor material of another conduction type, wherein the region is under the metal.

19. A silicon containing device, wherein the device is a semiconductor material with one or more p-n junctions formed after passivation of a surface of the semiconductor material, wherein a region of the passivated surface is modified from one semiconductor conduction type to another conduction type.

20. The device of claim 19, wherein the device is a diode.

21. The device of claim 19, wherein the device is a MOSFET.

22. A method for forming a device having one or more p-n junctions, the method comprising:

providing onto a surface of a substrate at least one atomic layer of a passivating agent to form a passivated surface, wherein the substrate is a semiconductor material of one conduction type;

depositing one or more metallic electrodes on the passivated surface and forming p-n junctions at the metal-substrate interface, wherein a region under the interface becomes a semiconductor material of another conduction type.

23. The method of claim 22, wherein the passivating agent minimizes electronic states bound to the surface.

24. The method of claim 22, wherein the substrate is n-type, the metal has a large work function and the region of the interface is p-type.

25. The method of claim 22, wherein the substrate is p-type, the metal has a small work function and the region of the interface is n-type.

26. The method of claim 22, wherein the passivating agent is selected from the group consisting of a Group V, VI, or VII cogener, or hydrogen.

27. The method of claim 22, wherein the passivating agent is selected from the group consisting of sulfur, selenium, and tellurium.

28. The method of claim 22, wherein the method occurs at a temperature below 700 degrees Centigrade.

29. The method of claim 22, further comprising forming a bottom surface ohmic contact on the substrate.

30. The method of claim 22 further comprising annealing for formation of a silicide on the bottom surface of the substrate.

31. The method of claim 22, wherein the method provides a discrete silicon device.

32. The method of claim 22, wherein the device is a diode.

33. The method of claim 22, wherein the region is under the deposited metallic electrodes.

34. A device having one or more p-n junctions, wherein the device is a discrete diode with one or more p-n junctions formed after passivation of a surface of the semiconductor material, wherein a region of the passivated surface is modified from one semiconductor conduction type to another conduction type.

35. A device having one or more p-n junctions, wherein the device is a discrete MOSFET with one or more p-n junctions formed after passivation of a surface of the semiconductor material, wherein a region of the passivated surface is modified from one semiconductor conduction type to another conduction type.

36. A method for forming a device having one or more p-n junctions, the method comprising:

providing onto an etched surface of a substrate at least one atomic layer of a passivating agent to form a passivated surface, wherein the substrate is a semiconductor material of one conduction type, wherein one or more portions of the surface are layered with silicon dioxide, a first metal, and at least one dielectric layer;

depositing a second metal on the passivated surface and layered portions of the surface forming one or more p-n junction at the second metal-substrate interface, wherein a region under the interface becomes a semiconductor material of another conduction type.

37. The method of claim 36, wherein the method further comprises patterning the second metal.

38. The method of claim 36, wherein the method further comprises forming source and drain electrodes.

39. The method of claim 38, wherein a gate is electrically insulated from the source and drain.

40. The method of claim 36, wherein the substrate is n-type, the second metal has a large work function and the region of the interface is p-type.

41. The method of claim 36, wherein the substrate is p-type, the second metal has a small work function and the region of the interface is n-type.

42. The method of claim 36, wherein the method occurs at a temperature below 700 degrees Centigrade.