CURRENT SOURCE CIRCUIT AND DESIGN METHODOLOGY

• US 20070262795A1
• Filed: 04/30/2007
• Published: 11/15/2007
• Est. Priority Date: 04/28/2006
• Status: Active Grant

• Current Assignee: Alyssa Apsel, Anand Pappu
• Original Assignee: Alyssa Apsel, Anand Pappu
• Inventors: Pappu, Anand, Apsel, Alyssa
• Granted Patent: US 7,629,832 B2
• Time in Patent Office: Days
• US Class Current: 327/103
• CPC Class Codes: G05F 1/561 Voltage to current converters amplifiers H03F

Abstract

A method of designing a current source involves selecting an equation for a current output through a circuit. Variations in current are checked to make sure they are not a strong function of process and bias. A circuit topology is then created as a function of the equation. Example circuits include an addition based current source and a square root based current source.

Claims

1. An addition based process invariant voltage to current converter comprising:

a first and a second transistor having inputs coupled to a voltage input;

an output of the first transistor coupled to a current output;

an output of the second transistor coupled to an input of a feedback transistor and to a voltage source through a resistor; and

wherein an output of the feedback transistor is coupled to the current output such that variations of current from the outputs of the first and feedback transistors substantially offset each other.

2. The current converter of claim 1 wherein the first, second and feedback transistors are coupled to ground.

3. The current converter of claim 1 wherein the resistor value is selected to minimize a standard deviation over mean of the output current.

4. The current converter of claim 1 wherein the elements are coupled such that fabrication variations induce opposite changes in the current from the outputs of the first and feedback transistors.

5. The current converter of claim 1 wherein the voltage input is coupled to a PTAT (proportional to absolute temperature) voltage source that ensures the current output is temperature compensated.

21. The method of claim 11 and further comprising fabricating the circuit topology as part of a larger integrated circuit on a die or wafer.

6. A square root based process invariant voltage to current converter comprising:

a first and a second transistor having inputs coupled to a voltage input;

an output of the second transistor coupled to a current output;

a current source coupled to an output of a third transistor;

an input of the third transistor coupled to a negative R cell feedback circuit and an output of the first transistor; and

wherein the current output is a function of the voltage input and feedback from the negative R cell such that variations of current substantially offset each other.

7. The current converter of claim 6 wherein the voltage input is coupled to a PTAT (proportional to absolute temperature) voltage source that ensures the current output is temperature compensated.

8. A square root based process invariant voltage to current converter comprising:

a translinear loop of first, second, third and fourth transistors;

a mathematical relation between the currents through the first transistor, current through the second transistor and the current through the third and fourth transistors;

a negative R cell attached to the first and second transistors which negatively correlates currents through the first and second transistors, wherein current output is a function of current fed to the first transistor and the negative-R cell such that variations of current substantially offset each other.

9. An integrated circuit comprising:

a first process invariant voltage to current converter having a gate coupled to a reference voltage and multiple transistors coupled such that fabrication variations induce opposite changes in the current from the transistors to provide the process invariant current; and

multiple further process invariant voltage to current converters having a gate coupled to the reference voltage and multiple transistors coupled such that fabrication variations induce opposite changes in the current from the transistors to provide the process invariant current, which is process invariant across the circuit when formed in various locations on a die or wafer.

10. The integrated circuit of claim 9 wherein the reference voltage comprises a PTAT (proportional to absolute temperature) voltage source that ensures the current is temperature compensated.

11. A method of designing a current source, the method comprising:

selecting an equation for a current output through a circuit;

ensuring variations in current are not a strong function of process and bias; and

deriving a circuit topology as a function of the equation.

12. The method of claim 11 and further comprising ensuring that the equation is dimensionally correct.

13. The method of claim 12 and further comprising selecting values for components of the circuit to minimize a standard deviation over mean of the output current.

14. The method of claim 12 wherein the current source is an addition based current source.

15. The method of claim 14 wherein a value for a resistor is selected to minimize a standard deviation over mean of the output current.

16. The method of claim 15 wherein transistors may have different sizes.

17. The method of claim 11, wherein the circuit topology may be used across a die to mirror currents while minimizing variations due to threshold and kappa mismatches.

18. The method of claim 11 wherein the current source is a square root based current source.

19. The method of claim 11 wherein the equation combines at least two currents such that variations in the currents offset each other to provide a process invariant output current.

20. The method of claim 19 wherein the circuit topology includes feedback to account for process induced current variations between the at least two currents.

22. A circuit fabricated from the circuit topology derived in claim 11.

23. A method of designing an electrical source, the method comprising:

selecting an equation for an output through a circuit;

ensuring variations in output are not a strong function of process and bias; and

creating a circuit topology as a function of the equation.

24. The method of claim 23 wherein the electrical source comprises a current source or a voltage source.

25. The method of claim 23 and further comprising fabricating the circuit topology as part of a larger integrated circuit on a die or wafer.

26. A circuit with an electrical source fabricated from the circuit topology derived in claim 23.