Voltage regulator for microelectronic devices using dual edge pulse width modulated control signal

• US 20070262802A1
• Filed: 05/12/2006
• Published: 11/15/2007
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Deval, Anant, Greiner, Robert, Burton, Edward, Huard, Doug
• Granted Patent: US 7,466,176 B2
• Time in Patent Office: Days
• US Class Current: 327/172
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel

Abstract

A voltage regulator is described for microelectronic devices using dual edge pulse width modulated control signal. In one example a first digital duty cycle value is received from a voltage controller and a pulse width modulated waveform is generated in response to the first duty cycle value, the waveform comprising a plurality of pulses with a modulated width. The waveform is applied to a voltage generator to generate a supply of power at a voltage determined by the duty cycle of the waveform. A second digital duty cycle value is received from the controller, and the leading edge of a subsequent pulse of the waveform is advanced if the second digital duty cycle value is greater than the first digital duty cycle. The trailing edge of the subsequent pulse of the waveform is advanced if the second digital duty cycle value is less than the first digital duty cycle value

Claims

1. A method comprising:

receiving a first digital duty cycle value from a voltage controller;

generating a pulse width modulated waveform in response to the first duty cycle value, the waveform comprising a plurality of pulses with a modulated width;

applying the waveform to a voltage generator to generate a supply of power at a voltage determined by the duty cycle of the waveform;

receiving a second digital duty cycle value from the controller;

advancing the leading edge of a subsequent pulse of the waveform if the second digital duty cycle value is greater than the first digital duty cycle; and

advancing the trailing edge of the subsequent pulse of the waveform if the second digital duty cycle value is less than the first digital duty cycle value.

2. The method of claim 1, further comprising:

delaying the trailing edge of a current pulse of the waveform if the second digital duty cycle value is received during the current pulse and the second digital duty cycle is greater than the first digital duty cycle.

3. The method of claim 1, further comprising:

delaying the leading edge of a subsequent pulse of a subsequent pulse of the waveform if the second digital duty cycle value is less than the first digital duty cycle and the second digital duty cycle is received before the start of the subsequent pulse.

4. The method of claim 1, wherein advancing the leading edge of a subsequent pulse of the waveform comprise triggering the leading edge upon receipt of the second digital duty cycle.

5. An apparatus comprising:

a leading edge counter to determine a start time of a pulse of a pulse width modulated waveform, the waveform being applied to a digital voltage generator to supply power to an integrated circuit;

a comparator to advance the start time determined by the counter in the event of an increase in a duty cycle command;

a trailing edge counter to determine an end time of a pulse based on the duty cycle command.

6. The apparatus of claim 5, further comprising a subtractor to decrease the count of the trailing edge counter to compensate for the advance in the start time from the comparator.

7. The apparatus of claim 5, further comprising a switch to modify the count of the trailing edge counter if the duty cycle command changes after the start of the pulse.

8. The apparatus of claim 5, further comprising a subtractor to compare a new duty cycle command to a previous duty cycle command and a comparator to advance the start time if the duty cycle command is increased and to maintain the start time if the duty cycle is decreased.

9. The apparatus of claim 5, wherein the leading edge counter comprises a master counter, a start time register, and a comparator, the master counter being compared in the comparator to the start time register to determine a regular start time for the leading edge of a sequence of pulses.

10. A computer system comprising:

a power supply;

a voltage regulator coupled to the power supply to receive a direct current voltage and to generate a regulated voltage from the received voltage;

a microprocessor to receive the regulated voltage to power the microprocessor, the microprocessor having an integrated controller to sense the voltage of the regulated voltage, to generate a compensation signal in response to the sensed voltage and to generate a digital pulse width modulated waveform in a digital pulse width modulator to apply to the voltage regulator to adjust the regulated voltage, the pulse width modulated waveform being generated using a leading edge counter to determine a start time of a pulse of the pulse width modulated waveform, a comparator to advance the start time determined by the counter in the event of an increase in compensation signal, and a trailing edge counter to determine an end time of a pulse based on the compensation signal.

11. The system of claim 10, wherein the voltage regulator comprises a plurality of phases each to independently generate a regulated voltage to apply to the microprocessor and wherein the digital pulse width modulator comprises a plurality of trailing edge counters to independently produce a pulse width modulated waveform for each of the voltage regulator phase based on the compensation signal.

12. The system of claim 10, wherein the digital pulse width modulator further comprises a register to store a copy of the compensation signal at the leading edge of a pulse and a comparator to compare the compensation signal after the leading edge of the pulse and to advance the trailing edge of the pulse if the compensation signal is reduced.

13. The system of claim 10, wherein the digital pulse width modulator further comprises a subtractor to compare a current compensation signal to a previous compensation signal and a comparator to advance the leading edge of the pulse if the compensation signal is increased.