Clock with regulated duty cycle and frequency

• US 20070262826A1
• Filed: 04/26/2007
• Published: 11/15/2007
• Est. Priority Date: 04/26/2006
• Status: Active Grant

• Current Assignee: Ahmad Dowlatabadi
• Original Assignee: Ahmad Dowlatabadi
• Inventors: Dowlatabadi, Ahmad
• Granted Patent: US 8,264,266 B2
• Time in Patent Office: Days
• US Class Current: 331/185
• CPC Class Codes: G04F 5/00 Apparatus for producing preselected time intervals for use as timing standards generating clock signals for electric digital computers G06F1/04
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 4/08 having sawtooth shape
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

A power-supply-independent clock, with controlled T_High and T_Low that permits both frequency and duty cycle to be set simultaneously and independently. Depending upon the implementation, the control values can be varied for frequency and duty cycle as determined by the user, or can be dependent upon temperature, power supply variations, or any other variable within the system, design or device that includes the clock.

Claims

1. A clock generator circuit comprising

a first reference voltage for setting the portion of a clock period when the clock signal is high,

a second reference voltage for setting the portion of a clock period when the clock signal is low,

at least one voltage detector responsive to at least one of the first and second reference voltages,

a control block for receiving signals from the at least one voltage detector derived at least in part from the first and second reference voltages,

a timing circuit for selecting which of the reference voltages is applied to the control block, and

switch control signals generated by the control block for controlling the timing circuit.

2. The clock generator circuit of claim 1 wherein at least one of the first and second reference voltages is variable.

3. The clock generator circuit of claim 1 wherein the timing circuit includes at least one component across which either voltage or current varies with time.

4. The clock generator circuit of claim 3 wherein at least one of the time variant components is a capacitor.

5. The clock generator circuit of claim 4 wherein the value of the capacitor is variable.

6. The clock generator circuit of claim 1 wherein both the first and second reference voltages are variable.

7. The clock generator circuit of claim 1 wherein the at least one voltage detector comprises two voltage detectors.

17. The clock generator circuit of claim 1 wherein the at least one voltage detector is selected from a group comprising a voltage comparator, Schmitt trigger, an operational amplifier operating either open loop or with high gain through small feedback.

8. A clock generator circuit comprising

at least one voltage detector,

a timing circuit having an output which varies with time, the output providing one input to the at least one voltage detector,

a pair of reference voltages selectively applied as a second input to the at least one voltage detector, whereby the output out the voltage detector is determined by comparing the output of the timing circuit and the applied reference voltage, and

a control block responsive to the voltage detector for generating a clock output having a variable frequency and duty cycle, and for generating switch control signals for operating the timing circuit.

10. The clock generator circuit of claim 8 wherein at least one of the reference voltages is variable.

11. The clock generator circuit of claim 8 wherein the timing circuit includes a current source.

12. The clock generator circuit of claim 8 wherein the timing circuit has a time constant.

13. The clock generator circuit of claim 12 wherein the time constant is variable to adjust frequency and duty cycle of an output clock signal.

18. The clock generator circuit of claim 8 wherein the at least one voltage detector is selected from a group comprising a voltage comparator, Schmitt trigger, an operational amplifier operating either open loop or with high gain through small feedback.

9. A clock generator circuit comprising

a timing circuit having an output that varies with time,

a first reference signal,

a second reference signal,

a first voltage detector for comparing the first reference signal and the output of the timing circuit,

a second voltage detector for comparing the second reference signal and the output of the timing circuit, and

a control block, responsive to outputs from the first and second voltage detectors, for forming an output clock signal and generating at least one timing control signal for selectively applying charge to the timing circuit.

14. The clock generator circuit of claim 9 wherein at least one of the reference voltages is variable.

15. The clock generator circuit of claim 9 wherein the timing circuit has a time constant.

16. The clock generator circuit of claim 15 wherein varying the time constant varies at least one of the frequency or the duty cycle of the output clock signal.

19. The clock generator circuit of claim 9 wherein the at least one voltage detector is selected from a group comprising a voltage comparator, Schmitt trigger, an operational amplifier operating either open loop or with high gain through small feedback.