I/O bus for analog sensors in an IC

• US 20070262879A1
• Filed: 05/12/2006
• Published: 11/15/2007
• Est. Priority Date: 05/12/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Deval, Anant, Greiner, Robert, Burton, Edward, Huard, Doug
• Application Number:
  US11/432,869
• Publication Number:
  US 20070262879A1
• Time in Patent Office: Days
• US Class Current: 340/870.210
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

An input/output bus for analog sensors in an integrated circuit is described. In one example, a plurality of analog sensors generate an analog output in response to a respective event on the integrated circuit. A plurality of digitizers each coupled to an analog sensor generate a digital representation of the analog output of the respective sensor, and a communications bus coupled to the plurality of digitizers communicates the digital representations to an external device.

Claims

1. An integrated circuit comprising

a plurality of analog sensors to generate an analog output in response to a respective event on the integrated circuit;

a plurality of digitizers each coupled to an analog sensor to generate a digital representation of the analog output of the respective sensor; and

a communications bus coupled to the plurality of digitizers to communicate the digital representations to an external device.

2. The integrated circuit of claim 1, wherein the digitizers each transmit the respective digital representation to the communications bus at an assigned time.

3. The integrated circuit of claim 1, wherein the analog sensors generate the respective analog output at a respective assigned time.

4. The integrated circuit of claim 1, wherein the integrated circuit comprises a plurality of processing cores, and wherein the communications bus comprises a feed bus for each core and an output bus to receive the digital representations for each feed bus and communicate the combined digital representations to an external device.

5. The integrated circuit of claim 1, wherein the communications bus comprises a plurality of OR circuits coupled between each digitizer and the bus to apply the digital representation from the respective digitizer when there is no other digital representation on the bus.

6. The integrated circuit of claim 1, further comprising a bus control unit coupled to the bus to receive the digital representations and convert them to a pin signaling protocol.

7. The integrated circuit of claim 1, wherein at least one analog sensor comprises a temperature sensor.

8. The integrated circuit of claim 1, wherein at least one analog sensor comprises a lock indication signal for a phase locked loop.

9. The integrated circuit of claim 1, wherein at least one analog sensor comprises a power status indicator.

10. The integrated circuit of claim 1, further comprising a plurality of consumers coupled to the bus, the consumers receiving a digital value on the bus and applying the digital value to a register in place of a sensed value.

11. The integrated circuit of claim 10, wherein the register comprises a temperature sensor register.

12. The integrated circuit of claim 1, wherein the communications is bidirectional to apply an external input data to the integrated circuit.

13. The integrated circuit of claim 12, wherein the external input data replaces an output of at least one of the plurality of analog sensors that is used internally by the integrated circuit.

14. A computer system comprising:

a microprocessor;

a socket interface on the microprocessor;

a plurality of analog sensors on the microprocessor to generate an analog output in response to a respective event on the integrated circuit;

a plurality of digitizers on the microprocessor each coupled to an analog sensor to generate a digital representation of the analog output of the respective sensor;

a communications bus on the microprocessor coupled to the plurality of digitizers;

a motherboard having a socket to receive the socket interface; and

a communications port on the motherboard to connect to the communications bus through the socket interface.

15. The computer system of claim 14, further comprising a power supply on the motherboard to supply power to the microprocessor based on digital representations received on the communications port.

16. The computer system of claim 14, further comprising a plurality of time slot synchronizers on the microprocessor, each coupled to a digitizer to time the application of the respective digital representation on the communications bus.

17. A method comprising:

sensing analog data at a plurality of locations in an integrated circuit;

digitizing the sensed analog data;

applying the digitized analog data from each of the plurality of locations to a common sensor bus, the data from each location being applied to the bus at a different time.

18. The method of claim 17, further comprising:

applying data to the common sensor bus from an external source;

receiving the applied data at a plurality of consumers in the integrated circuit at a predefined time for each consumer; and

applying the received data at each consumer as if the data were sensed by a corresponding analog sensor.

19. The method of claim 18 wherein the data from the external source comprises data corresponding to simulations of sensed analog data.

20. The method of claim 19, further comprising applying the received data to a logic simulator during a test to test internal functions of the integrated circuit.