THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY
First Claim
1. A monolithic integrated circuit comprising:
- a three-dimensional memory array having at least two memory planes, each memory plane comprising a respective plurality of segmented array lines of a first type and further comprising a respective plurality of segment switch devices; and
a plurality of global array lines on at least one layer of the memory array;
each segment switch device for coupling a segmented array line of the first type to an associated global array line.
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Accused Products
Abstract
A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
104 Citations
46 Claims
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1. A monolithic integrated circuit comprising:
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a three-dimensional memory array having at least two memory planes, each memory plane comprising a respective plurality of segmented array lines of a first type and further comprising a respective plurality of segment switch devices; and
a plurality of global array lines on at least one layer of the memory array;
each segment switch device for coupling a segmented array line of the first type to an associated global array line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A monolithic integrated circuit comprising:
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a three-dimensional memory array having at least two memory planes and further having a respective plurality of word lines on each of at least one layer of the memory array, having a respective plurality of bit line segments on each of at least one layer of the memory array, each memory plane comprising a vertically adjacent word line layer and segmented bit line layer, each memory plane comprising a plurality of memory segments;
a respective plurality of global bit lines on each of at least a first global bit line layer;
wherein each memory segment comprises a bit line segment and a segment switch device for coupling the bit line segment to an associated global bit line. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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Specification