Internal voltage generation circuit for semiconductor device

• US 20070263468A1
• Filed: 12/27/2006
• Published: 11/15/2007
• Est. Priority Date: 05/10/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Im, Jae-Hyuk, Ko, Jae-Bum
• Granted Patent: US 7,564,732 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

Provided is an internal voltage generation circuit for generating an internal voltage used in a semiconductor device. The internal voltage generation circuit includes a standby internal voltage generator which is driven during a standby operation and an active operation and supplies a voltage to a core voltage end, a first active internal voltage generator for supplying a voltage to the core voltage end in response to an active signal activated during the active operation, and a second active internal voltage generator which is driven only for a predetermined time period in response to the active signal, and supplies a voltage to the core voltage end.

Claims

1. An internal voltage generation circuit for use in a semiconductor device, comprising:

a standby internal voltage generator which is to be driven during a standby operation and an active operation, and supplies a voltage to an internal voltage end;

a first active internal voltage generator for supplying a voltage to the internal voltage end in response to an active signal being activated during the active operation; and

a second active internal voltage generator which is to be driven only for a predetermined time period in response to the active signal, and supplies a voltage to the internal voltage end.

2. The internal voltage generation circuit as recited in claim 1, wherein the second active internal voltage generator includes:

an active signal sensing circuit for sensing the active signal; and

an internal voltage generator for generating a voltage in response to an output signal of the active signal sensing circuit.

3. The internal voltage generation circuit as recited in claim 2, wherein the active signal sensing circuit is provided with a pulse generator for generating a pulse signal which becomes active only for the predetermined time period after receiving the active signal.

4. The internal voltage generation circuit as recited in claim 3, wherein the pulse generator includes:

a delay circuit for taking and delaying the active signal; and

an output circuit for receiving the active signal and an output signal of the delay circuit to provide the pulse signal.

5. The internal voltage generation circuit as recited in claim 4, wherein the delay circuit is constituted by an inverter chain.

6. The internal voltage generation circuit as recited in claim 3, wherein the pulse generator divides an internal clock signal in response to the active signal to output the pulse signal.

7. The internal voltage generation circuit as recited in claim 2, wherein the internal voltage generator includes:

a voltage comparison circuit for comparing the voltage supplied to the internal voltage end with a reference voltage in response to an output signal of the active signal sensing circuit;

a pull-up driver for supplying an external voltage to the internal voltage end in response to an output signal of the voltage comparison circuit; and

a switch for turning off the pull-up driver in response to an output signal of the active signal sensing circuit.

8. The internal voltage generation circuit as recited in claim 7, wherein the voltage comparison circuit includes:

a voltage comparator composed of a current mirror type differential amplifier receiving the voltage to the internal voltage end and the reference voltage; and

a MOS transistor for taking an output signal of the active signal sensing circuit via a gate.

9. The internal voltage generation circuit as recited in claim 8, wherein the pull-up driver is provided with a MOS transistor which is connected between the internal voltage end and an external voltage end, and takes an output signal of the voltage comparator via a gate.

10. The internal voltage generation circuit as recited in claim 7, wherein the switch is provided with a MOS transistor which is connected between an output end of the voltage comparison circuit and an external voltage end, and receives an output signal of the active signal sensing circuit via a gate.

11. The internal voltage generation circuit as recited in claim 1, wherein the predetermined time period is tRAS.

12. An internal voltage generation method for use in a semiconductor device, comprising the steps of:

supplying a voltage to a supply end by driving a standby internal voltage generator, and a first and a second active internal voltage generators during an active operation; and

stopping the driving of the second active internal voltage generator after a predetermined time period, and supplying a voltage to the supply end by continuing to drive the standby internal voltage generator and the first active internal voltage generator.

13. The method of claim 12 further comprising:

employing the internal voltage generated by the internal voltage generation method in said semiconductor device.

14. An internal voltage generation circuit, comprising:

a first active internal voltage generator for supplying an internal voltage during an active operation; and

a second active internal voltage generator for supplying the internal voltage for a predetermined time,

wherein the predetermined time is included in the active operation.

15. The internal voltage generation circuit as recited in claim 14, wherein the second active internal voltage generator includes:

an active signal sensing circuit for sensing the active signal; and

an internal voltage generator for generating a voltage in response to an output signal of the active signal sensing circuit.

16. The internal voltage generation circuit as recited in claim 15, wherein the active signal sensing circuit is provided with a pulse generator for generating a pulse signal which becomes active only for the predetermined time period after receiving the active signal.

17. The internal voltage generation circuit as recited in claim 16, wherein the pulse generator includes:

a delay circuit for taking and delaying the active signal; and

an output circuit for receiving the active signal and an output signal of the delay circuit to provide the pulse signal.

18. The internal voltage generation circuit as recited in claim 17, wherein the delay circuit is constituted by an inverter chain.

19. The internal voltage generation circuit as recited in claim 16, wherein the pulse generator divides an internal clock signal in response to the active signal to output the pulse signal.

20. The internal voltage generation circuit as recited in claim 15, wherein the internal voltage generator includes:

a voltage comparison circuit for comparing the voltage supplied to the internal voltage end with a reference voltage in response to an output signal of the active signal sensing circuit;

a pull-up driver for supplying an external voltage to the internal voltage end in response to an output signal of the voltage comparison circuit; and

a switch for turning off the pull-up driver in response to an output signal of the active signal sensing circuit.

21. The internal voltage generation circuit as recited in claim 20, wherein the voltage comparison circuit includes:

a voltage comparator composed of a current mirror type differential amplifier receiving the voltage to the internal voltage end and the reference voltage; and

a MOS transistor for taking an output signal of the active signal sensing circuit via a gate.

22. The internal voltage generation circuit as recited in claim 21, wherein the pull-up driver is provided with a MOS transistor which is connected between the internal voltage end and an external voltage end, and takes an output signal of the voltage comparator via a gate.

23. The internal voltage generation circuit as recited in claim 20, wherein the switch is provided with a MOS transistor which is connected between an output end of the voltage comparison circuit and an external voltage end, and receives an output signal of the active signal sensing circuit via a gate.

24. The internal voltage generation circuit as recited in claim 14, wherein the predetermined time period is tRAS.