Methods and systems for DSP-based receivers

• US 20070263673A1
• Filed: 07/16/2007
• Published: 11/15/2007
• Est. Priority Date: 07/21/2000
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gopinathan, Venugopal, Agazzi, Oscar
• Granted Patent: US 7,778,286 B2
• Time in Patent Office: Days
• US Class Current: 370/516
• CPC Class Codes: H03M 1/0604 at one point, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/0609 at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error
• CPC Class Codes: H03M 1/0624 by synchronisation
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H04B 10/6933 Offset control of the differential preamplifier
• CPC Class Codes: H04B 10/697 Arrangements for reducing noise and distortion
• CPC Class Codes: H04B 10/6971 using equalisation
• CPC Class Codes: H04L 2025/03445 Time domain
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03133 with a non-recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03203 Trellis search techniques
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

Claims

1. A method for receiving data signals, comprising:

(a) receiving a data signal;

(b) generating N sampling signals, each of said N sampling signals having an associated phase;

(c) controlling N analog-to-digital converter (“

ADC”

) paths with said N sampling signals to sample said data signal at said phases;

(d) individually adjusting said N sampling signals to reduce phase errors between said received data signal and each of said N sampling signals in said N ADC paths; and

(e) generating a digital signal representative of said received data signal from samples received from said N ADC paths.

2. The method according to claim 1, wherein step (d) further comprises the step of individually adjusting for offsets in each of said N ADC paths.

3. The method according to claim 2, wherein step (d) further comprises the step of measuring said offsets in a digital domain and individually adjusting for said offsets in said digital domain for each of said N ADC paths.

4. The method according to claim 3, wherein step (d) further comprises the step of measuring said offsets in an M-path parallel decision feedback equalizer (“

DFE”

) and individually adjusting one or more DFE DC taps associated with each of said N ADC paths.

5. The method according to claim 2, wherein step (d) further comprises the step of measuring said offsets in a digital domain and individually adjusting for said offsets in an analog domain for each of said N ADC paths.

6. The method according to claim 5, wherein step (d) further comprises the step of measuring said offsets in an M-path parallel decision feedback equalizer (“

DFE”

) and individually adjusting analog compensation in each of said N ADC paths.

7. The method according to claim 2, wherein step (d) further comprises the step of measuring said offsets in an analog domain and individually adjusting for said offsets in said analog domain for each of said N ADC paths.

8. The method according to claim 1, wherein step (d) further comprises the step of individually adjusting for gain errors in said N-ADC paths.

9. The method according to claim 8, wherein step (d) further comprises the step of measuring said gain errors in a digital domain and individually adjusting for said gain errors in said digital domain for each of said N ADC paths.

10. The method according to claim 9, wherein step (d) further comprises the step of measuring said gain errors in an M-path parallel feed-forward equalizer (“

FFE”

) and individually adjusting one or more FFE gain taps associated with each of said N ADC paths.

11. The method according to claim 8, wherein step (d) further comprises the step of measuring said gain errors in a digital domain and individually adjusting for said gain errors in an analog domain for each of said N ADC paths.

12. The method according to claim 11, wherein step (d) further comprises the step of generating digital control signals for each of said N ADC paths and individually adjusting programmable gain amplifiers associated with said N ADC paths under control of digital control signals.

13. The method according to claim 1, wherein step (d) comprises generating a decision-directed error signal, and step (e) comprises individually adjusting one or more parameters for each of said N ADC paths to reduce said decision-directed error signal.

14. The method according to claim 1, wherein step (d) comprises performing an equalization process to compensate for one or more of:

(i) cross-talk;

(ii) inter-symbol interference;

(iii) attenuation; and

(iv) noise.

15. A receiver, comprising:

a receiver input;

an analog-to-digital converter (“

ADC”

) array of N ADC paths, each said N ADC paths including coupled to said receiver input;

an M-path DSP coupled to said ADC array, said M-path DSP having a timing recovery module, wherein said timing recovery module provides N sampling clocks to said N ADC paths, whereby said N sampling clocks control said N ADC paths to sample a received signal at said receiver input; and

means for adjusting each of said N sampling signals to reduce sampling phase errors in said N ADC paths.

16. The receiver according to claim 15, wherein said means for adjusting comprises N timing recovery loops, each of said N timing recovery loops coupled to a corresponding one of said N ADC paths, whereby each said timing recovery loop determines a sampling phase error in said corresponding one of said N ADC paths and individually adjusts a corresponding one of said N sampling signals to reduce said sampling phase error.

17. The receiver according to claim 15, wherein said means for adjusting comprises means for individually adjusting for offsets in said N ADC paths.

18. The receiver according to claim 17, wherein said means for adjusting comprises digital measuring means for measuring said offsets and digital adjusting means for individually adjusting for said offsets.

19. The receiver according to claim 18, wherein said digital measuring means comprises an M-path parallel decision feedback equalizer (“

DFE”

) in said M-path DSP, and wherein said digital adjusting means comprises one or more DFE DC taps associated with each of said N ADC paths.

20. The receiver according to claim 17, wherein said means for adjusting comprises digital measuring means for measuring said offsets and analog adjusting means for individually adjusting for said offsets.

21. The receiver according to claim 20, wherein said digital measuring means comprises an M-path parallel decision feedback equalizer (“

DFE”

) in said M-path DSP, and wherein said analog adjusting means comprises means for individually adjusting analog compensation in each of said N ADC paths.

22. The receiver according to claim 17, wherein said means for adjusting comprises analog measuring means for measuring said offsets and analog adjusting means for individually adjusting for said offsets.

23. The receiver according to claim 15, wherein said means for adjusting further comprises means for individually adjusting for gain errors in said N ADC paths.

24. The receiver according to claim 23, wherein said means for individually adjusting for gain errors in said N ADC paths comprises digital measuring means for measuring said gain errors and digital adjusting means for individually adjusting for said gain errors.

25. The receiver according to claim 23, wherein said means for individually adjusting for gain errors in said N ADC paths comprises digital measuring means for measuring said gain errors and analog adjusting means for individually adjusting for said gain errors.

26. The receiver according to claim 15, wherein said means for adjusting comprises a feed-forward equalizer implemented as a phase interpolator to individually adjust said N sampling signals.