Method of Making a MOS-Gated Transistor with Reduced Miller Capacitance
First Claim
1. A method of forming a trench MOS-gated transistor, the method comprising:
- providing a first region of a first conductivity type;
forming a well region of a second conductivity type in an upper portion of the first region;
forming a trench extending through the well region and terminating within the first region, portions of the well region extending along the trench sidewalls forming channel regions; and
implanting dopants of the second conductivity type along predefined portions of the bottom of the trench to form a plurality of second regions extending deeper than a bottom surface of the well region, each of the plurality of second regions being contiguous with the well region such that when the transistor is in an on state the plurality of second regions prevent a current from flowing through those channel region portions located directly above the plurality of second regions.
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Accused Products
Abstract
A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first region. Dopants of the second conductivity type are implanted along predefined portions of the bottom of the trench to form regions along the bottom of the trench which are contiguous with the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.
105 Citations
16 Claims
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1. A method of forming a trench MOS-gated transistor, the method comprising:
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providing a first region of a first conductivity type;
forming a well region of a second conductivity type in an upper portion of the first region;
forming a trench extending through the well region and terminating within the first region, portions of the well region extending along the trench sidewalls forming channel regions; and
implanting dopants of the second conductivity type along predefined portions of the bottom of the trench to form a plurality of second regions extending deeper than a bottom surface of the well region, each of the plurality of second regions being contiguous with the well region such that when the transistor is in an on state the plurality of second regions prevent a current from flowing through those channel region portions located directly above the plurality of second regions. - View Dependent Claims (2, 3, 4)
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5. A method of forming a trench MOS-gated transistor, the method comprising:
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providing a silicon substrate;
forming a silicon epitaxial layer of a first conductivity type over the substrate;
forming a well region of a second conductivity type in an upper portion of the silicon epitaxial layer;
forming a trench extending through the well region and terminating within the epitaxial silicon layer;
implanting dopants of the second conductivity type along the bottom of the trench to form a region of the second conductivity type extending along a bottom portion of the trench such that a gap is formed between the silicon region and the well region through which gap a current flows when the transistor is in an on state;
forming source regions of the first conductivity type flanking each side of the trench, whereby potions of the well region extending along outer sidewalls of each of the plurality of gate trenches form channel regions; and
filling the trench with a polysilicon material at least up to and partially overlapping with the source regions. - View Dependent Claims (6, 7)
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8. A method of forming a trench MOS-gated transistor, the method comprising:
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providing a first region of a first conductivity type;
performing a shallow implant of dopants of a second conductivity type into the first region;
performing a deep implant of dopant of the second conductivity type into the first region;
performing a temperature cycle after the deep and shallow implant steps to drive the respective implanted dopants deeper into the first region to thereby form a well region corresponding to the shallow implant and a second region corresponding to the deep implant, the deepest portion of the second region being deeper than a bottom surface of the well region; and
forming a trench having a first portion extending through the well region and terminating within the first region and a second portion extending through the well region and terminating within the second region. - View Dependent Claims (9, 10, 11, 12)
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13. A method of forming a trench MOS-gated transistor, the method comprising:
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providing a first region of a first conductivity type;
performing a shallow implant of dopants of a second conductivity type into the first region;
performing a temperature cycle to drive the implanted dopants deeper into the first region;
performing a second implant of dopants of the second conductivity type into the first region;
performing a temperature cycle to drive the implanted dopants from the second implant step deeper into the silicon region and to drive the dopants from the shallow implant step even deeper into the silicon to thereby form a well region corresponding to the second implant and a second region corresponding to the shallow implant, the deepest portion of the second region being deeper than a bottom surface of the well region; and
forming a trench having a first portion extending through the well region and terminating within the silicon region and a second portion extending through the well region and terminating within the second region - View Dependent Claims (14, 15, 16)
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Specification