Methods of forming trench isolation and methods of forming arrays of FLASH memory cells

• US 20070264794A1
• Filed: 05/11/2006
• Published: 11/15/2007
• Est. Priority Date: 05/11/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Li, Li
• Granted Patent: US 7,682,977 B2
• Time in Patent Office: Days
• US Class Current: 438/439
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is deposited and solidified within the isolation trenches to form a solidified dielectric within the isolation trenches. The dielectric comprises carbon and silicon, and can be considered as having an elevationally outer portion and an elevationally inner portion within the isolation trenches. At least one of carbon removal from and/or oxidation of the outer portion of the solidified dielectric occurs. After such, the dielectric outer portion is etched selective to and effective to expose the dielectric inner portion. After the etching, dielectric material is deposited over the dielectric inner portion to within the isolation trenches.

Claims

1. A method of forming trench isolation, comprising:

providing isolation trenches within a semiconductor substrate;

depositing and solidifying a liquid within the isolation trenches to form a solidified dielectric within the isolation trenches, the dielectric comprising carbon and silicon, the dielectric comprising an elevationally outer portion and an elevationally inner portion within the isolation trenches;

removing carbon from the outer portion of the solidified dielectric;

after the removing, etching the dielectric outer portion selective to and effective to expose the dielectric inner portion; and

after the etching, depositing dielectric material over the dielectric inner portion to within the isolation trenches.

2. The method of claim 1 wherein carbon content in the solidified dielectric is from 5 atomic percent to 70 atomic percent.

4. The method of claim 1 wherein silicon content in the solidified dielectric is from 10 atomic percent to 90 atomic percent.

7. The method of claim 1 wherein carbon content in the solidified dielectric is from 20 atomic percent to 40 atomic percent, and silicon content in the solidified dielectric is from 30 atomic percent to 40 atomic percent.

8. The method of claim 1 wherein the liquid comprises at least one of nitrogen and oxygen.

14. The method of claim 1 wherein the liquid comprises an organosiloxane.

15. The method of claim 1 wherein the liquid comprises a silicate polymer.

16. The method of claim 1 wherein carbon is removed from said outer portion to leave no more than 5 atomic percent carbon in said outer portion.

21. The method of claim 1 wherein the removing also oxidizes said outer portion.

22. The method of claim 1 wherein the removing comprises exposure to an oxygen-containing material.

24. The method of claim 1 wherein the removing comprises exposure to an oxygen-containing plasma.

25. The method of claim 1 wherein the semiconductor substrate comprises semiconductive material having an outermost surface, the outer portion from which carbon is removed being from 50 Angstroms to 3,000 Angstroms deep within said semiconductor substrate relative to said outermost surface.

27. The method of claim 1 wherein the etching comprises wet etching.

28. The method of claim 1 wherein the etching comprises dry etching.

30. The method of claim 1 wherein the etching the dielectric outer portion selective to the dielectric inner portion is at a selectivity ratio of at least 5:

1 upon exposure of the dielectric inner portion.

31. The method of claim 1 wherein the etching the dielectric outer portion selective to the dielectric inner portion is at a selectivity ratio of at least 100:

1 upon exposure of the dielectric inner portion.

32. The method of claim 1 comprising after the etching and before the depositing of the dielectric material, removing carbon from the inner portion of the solidified dielectric.

33. The method of claim 32 wherein carbon is removed from said inner portion to leave no more than 5 atomic percent carbon in said inner portion.

34. The method of claim 32 wherein carbon is removed from said inner portion to leave no more than 2.5 atomic percent carbon in said inner portion.

35. The method of claim 32 wherein carbon is removed from said inner portion to leave no more than 1.0 atomic percent carbon in said inner portion.

36. The method of claim 32 wherein carbon is removed from said inner portion to leave no more than 0.5 atomic percent carbon in said inner portion.

37. The method of claim 32 wherein no detectable carbon remains in said inner portion after said removing of carbon from said inner portion.

38. The method of claim 1 comprising forming gate dielectric material and floating gate material over the semiconductor substrate prior to depositing said liquid.

39. The method of claim 1 comprising forming gate dielectric material and floating gate material over the semiconductor substrate prior to providing the isolation trenches.

40. The method of claim 1 comprising forming floating gate transistors of NAND unit cells of an array of NAND memory circuitry intermediate adjacent pairs of the isolation trenches.

3. (canceled)

5-6. -6. (canceled)

9-13. -13. (canceled)

17-20. -20. (canceled)

23. (canceled)

26. (canceled)

29. (canceled)

41. A method of forming trench isolation, comprising:

providing isolation trenches within a semiconductor substrate;

depositing and solidifying a liquid within the isolation trenches to form a solidified dielectric within the isolation trenches, the dielectric comprising carbon and silicon, the dielectric comprising an elevationally outer portion and an elevationally inner portion within the isolation trenches;

oxidizing the outer portion of the solidified dielectric;

after the oxidizing, etching the dielectric outer portion selective to and effective to expose the dielectric inner portion; and

after the etching, depositing dielectric material over the dielectric inner portion to within the isolation trenches.

42-48. -48. (canceled)

49. A method of forming trench isolation, comprising:

providing isolation trenches within a semiconductor substrate;

depositing and solidifying a liquid within the isolation trenches to form a solidified dielectric within the isolation trenches, the liquid comprising an oganosiloxane, the dielectric comprising an elevationally outer portion and an elevationally inner portion within the isolation trenches;

removing carbon from the outer portion of the solidified dielectric and oxidizing the outer portion of the solidified dielectric, the removing and oxidizing comprising exposure to an oxygen-containing material, the carbon being removed from said outer portion to leave no more than 1.0 atomic percent carbon in said outer portion;

after the removing and the oxidizing, etching the dielectric outer portion selective to and effective to expose the dielectric inner portion using an aqueous HF-comprising solution;

after the etching, removing carbon from the inner portion of the solidified dielectric to leave no more than 1.0 atomic percent carbon in said inner portion; and

after removing carbon from the inner portion, depositing dielectric material over the dielectric inner portion to within the isolation trenches.

50-53. -53. (canceled)

54. A method of forming an array of FLASH memory cells, comprising:

forming a gate dielectric over a semiconductor substrate;

forming floating gate material over the gate dielectric;

forming trench isolation masking material over the floating gate material;

forming a series of alternating active area rows and isolation trenches using the trench isolation masking material as a mask, said active area rows having said gate dielectric and floating gate material thereover;

depositing and solidifying a liquid within the isolation trenches to form a solidified dielectric within the isolation trenches, the dielectric comprising carbon and silicon, the dielectric comprising an elevationally outer portion and an elevationally inner portion within the isolation trenches;

removing carbon from the outer portion of the solidified dielectric;

after removing the carbon, etching the dielectric outer portion selective to and effective to expose the dielectric inner portion;

after the etching, depositing dielectric material over the dielectric inner portion to within the isolation trenches;

removing the trench isolation masking material from over the floating gate material; and

after removing the trench isolation masking material, forming control gate dielectric material and control gate material over the floating gate material.

55. A method of forming an array of FLASH memory cells, comprising:

forming a gate dielectric over a semiconductor substrate;

forming floating gate material over the gate dielectric;

forming trench isolation masking material over the floating gate material;

forming a series of alternating active area rows and isolation trenches using the trench isolation masking material as a mask, said active area rows having said gate dielectric and floating gate material thereover;

depositing and solidifying a liquid within the isolation trenches to form a solidified dielectric within the isolation trenches, the dielectric comprising carbon and silicon, the dielectric comprising an elevationally outer portion and an elevationally inner portion within the isolation trenches;

oxidizing the outer portion of the solidified dielectric;

after the oxidizing, etching the dielectric outer portion selective to and effective to expose the dielectric inner portion;

after the etching, depositing dielectric material over the dielectric inner portion to within the isolation trenches;

removing the trench isolation masking material from over the floating gate material; and

after removing the trench isolation masking material, forming control gate dielectric material and control gate material over the floating gate material.

56. A method of forming an array of FLASH memory cells, comprising:

forming a gate dielectric over a semiconductor substrate;

forming floating gate material over the gate dielectric;

forming trench isolation masking material over the floating gate material;

forming a series of alternating active area rows and isolation trenches using the trench isolation masking material as a mask, said active area rows having said gate dielectric and floating gate material thereover;

depositing and solidifying a liquid within the isolation trenches to form a solidified dielectric within the isolation trenches, the liquid comprising an organosiloxane, the dielectric comprising carbon and silicon, the dielectric comprising an elevationally outer portion and an elevationally inner portion within the isolation trenches;

removing carbon from the outer portion of the solidified dielectric and oxidizing the outer portion of the solidified dielectric, the removing and oxidizing comprising exposure to an oxygen-containing material, the carbon being removed from said outer portion to leave no more than 1.0 atomic percent carbon in said outer portion;

after the removing and the oxidizing, etching the dielectric outer portion selective to and effective to expose the dielectric inner portion using an aqueous HF-comprising solution;

after the etching, removing carbon from the inner portion of the solidified dielectric to leave no more than 1.0 atomic percent carbon in said inner portion;

after removing carbon from the inner portion, depositing dielectric material over the dielectric inner portion to within the isolation trenches;

removing the trench isolation masking material from over the floating gate material; and

after removing the trench isolation masking material, forming control gate dielectric material and control gate material over the floating gate material.