Information Processing Apparatus Having Multiple Processing Units Sharing Multiple Resources

• US 20070266196A1
• Filed: 09/02/2005
• Published: 11/15/2007
• Est. Priority Date: 09/16/2004
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Torii, Sunao
• Granted Patent: US 7,650,453 B2
• Time in Patent Office: Days
• US Class Current: 710/309
• CPC Class Codes: G06F 13/1631 through address comparison
• CPC Class Codes: G06F 13/362 with centralised access control

Abstract

A technique for improving usage efficiency of a shared resource and improving processing capacity in an information processing apparatus, without increasing the transmission rate or the bit width of a bus is disclosed. Multiple bus interfaces are connected to at least one shared resource. The multiple bus interfaces are connected to a multi-layer bus respectively. Furthermore, data buffers for holding read data and write data respectively are provided for each bus interface. An arbiter arbitrates access requests from the respective bus interfaces, and the shared resource reads and writes data in response to the access request which has been given an access right.

Claims

1. An information processing apparatus comprising:

multiple information processing units;

a shared resource having multiple bus interfaces, each of which has a read buffer for temporarily holding read data to be returned in response to an access request from said information processing unit and a write buffer for temporarily holding write data received from said information processing unit, and an arbiter for arbitrating multiple access requests issued by said information processing unit, said shared resource being accessed by said information processing unit; and

a bus for connecting said information processing unit and said shared resource.

2. The information processing apparatus according to claim 1, wherein

said read buffer:

stores said read data from said shared resource at a processing speed of said shared resource, and sends said read data to said information processing unit at a transmission speed of said bus; and

said write buffer;

stores said write data received from said information processing unit at the transmission speed of said bus, and writes said write data to said shared resource at the processing speed of said shared resource.

3. The information processing apparatus according to claim 1, wherein said bus interface:

when said bus interface receives the access request from said information processing unit, compares an address of an access destination for said access request and an address of an access destination corresponding to data previously held in said read buffer and in said write buffer; and

if the access request is the access request with respect to the same address as the address of the access destination corresponding to the data held in said read buffer or in said write buffer, sends said access request to said arbiter, after storing said read data in said read buffer from said shared resource is completed, or after writing the write data held in said write buffer to said shared resource is completed.

4. The information processing apparatus according to claim 1, wherein

a predetermined priority is granted to said information processing unit, said read buffer or said write buffer;

and

said arbiter,

permits said access requests in the order according to said priority when said arbiter receives the multiple access requests with respect to said shared resource.

5. The information processing apparatus according to claim 4, wherein said bus interface:

if said bus interface receives the access request with respect to the same address as an address of an access destination corresponding to data held in said read buffer and in said write buffer, raises the priority of a process for reading said read data from said shared resource to said read buffer or a process for writing said write data to said shared resource from said write buffer.

6. The information processing apparatus according to claim 1, wherein said read buffer;

when it receives the access request from said information processing unit, compares an address of an access destination for said access request and an address of an access destination corresponding to the read data previously held in said read buffer, and

if the access request is the access request with respect to the same address as the address of the access destination corresponding to the read data held in said read buffer, returns the read data held in said read buffer to said information processing unit without reading said read data from said shared resource.

7. The information processing apparatus according to claim 1, wherein said write buffer:

when said write buffer receives the access request from said information processing unit, compares an address of an access destination for said access request and an address of an access destination corresponding to the write data previously held in said write buffer; and

if the access request is the access request with respect to an address continuous with the address of the access destination corresponding to the write data held in said write buffer, stores the write data retained in said write buffer and the write data received from said information processing unit together in said shared resource.

8. The information processing apparatus according to claim 1, wherein said multiple bus interfaces are commonly provided that correspond to multiple shared resources.

9. The information processing apparatus according to claim 1, wherein said multiple bus interfaces are based on different bus conventions respectively.

10. The information processing apparatus according to claim 1, wherein

said shared resource is a main memory with a SDRAM;

and

said arbiter knows a state of said SDRAM, and based on said state, determines the access request that is to be preferentially selected.

11. The information processing apparatus according to claim 10, wherein said arbiter preferentially selects the access request concerning which the number of arbitration operations has exceeded the predetermined number since the access request was issued, regardless of the state of said SDRAM.

12. The information processing apparatus according to claim 1, wherein when there is a access request, said multiple bus interfaces provided in one shared resource identify the information processing unit which has issued said access request;

and

said arbiter provided in said one shared resource has previously defined a priority with respect to each of said information processing units, and performs the arbitration according to said priority of the information processing unit identified by said bus interfaces.

13. The information processing apparatus according to claim 1, wherein when the information processing unit accessing said shared resource inhibits access with respect to said shared resource by other information processing units;

the access to said shared resource by, in addition to the bus interface used for the access by said information processing unit which has inhibited, other bus interfaces provided in said same shared resource in which said bus interface is provided, is inhibited.

14. The information processing apparatus according to claim 13, wherein only any one of said multiple bus interfaces provided in one shared resource has a function of inhibiting access with respect to said shared resource by other information processing units.

15. The information processing apparatus according to claim 1, wherein when the information processing unit accessing said shared resource inhibits the access with respect to a specific address area in said shared resource by other information processing units,

the access to said specific address area in said shared resource by, in addition to the bus interface used for the access by said information processing unit which has inhibited, other bus interfaces provided in said same shared resource in which said bus interface is provided, is inhibited.

16. The information processing apparatus according to claim 15, wherein only any one of said multiple bus interfaces provided in one shared resource has a function of inhibiting the access with respect to said shared resource by other information processing units.

17. The information processing apparatus according to claim 1, wherein said read buffer includes a through path for transferring data not via said read buffer, and returns the data from said shared resource to said information processing unit via said through path in a predetermined cycle.