Clock recovery system with triggered phase error measurement

• US 20070266275A1
• Filed: 04/19/2006
• Published: 11/15/2007
• Est. Priority Date: 04/19/2006
• Status: Active Grant

• Current Assignee: Keysight Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Stimple, James, Palko, Jady
• Granted Patent: US 7,571,339 B2
• Time in Patent Office: Days
• US Class Current: 714/700
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10222 clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation dedicated sync patterns in the modulation code G11B20/1403
• CPC Class Codes: G11B 20/14 using self-clocking codes
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A measurement system includes a clock recovery system and a measurement module coupled to the clock recovery system. The clock recovery system has an associated response characteristic. The clock recovery system receives an input signal and recovers a clock signal from the input signal. The measurement module is coupled to the clock recovery system and measures a phase error signal received from the clock recovery system, time-referenced to a trigger signal that is applied to the measurement module, where the phase error signal represents the phase difference between the input signal and the recovered clock signal. A processor applies the associated response characteristic to the measured phase error signal to determine the phase of the input signal.

Claims

1. A measurement system, comprising:

a clock recovery system having an associated response characteristic, receiving an input signal and recovering a clock signal from the input signal;

a measurement module coupled to the clock recovery system, measuring a phase error signal received from the clock recovery system that represents a phase error between the input signal and the recovered clock signal; and

a processor applying the associated response characteristic of the clock recovery system to the measured phase error signal to determine the phase of the input signal.

2. The measurement system of claim 1 wherein the clock recovery system includes a signal summer having a first input receiving a phase detected signal provided by a phase detector within a phase locked loop (PLL), and a signal source coupled to a second input of the signal summer selectively providing a stimulus signal to the signal summer.

3. The measurement system of claim 2 wherein the measurement module includes an analog-to-digital converter (ADC) coupled to a signal path between the signal summer and a loop integrator within the PLL.

4. The measurement system of claim 3 wherein the ADC measures a calibration error signal in the signal path with the signal source providing the stimulus signal to the signal summer, with the input signal applied to the phase detector, and with the PLL in a phase locked state, wherein the calibration error signal is processed to provide the response characteristic associated with the clock recovery system.

5. The measurement system of claim 4 wherein the stimulus signal includes at least one of a step signal and an impulse signal.

6. The measurement system of claim 4 wherein the response characteristic associated with the clock recovery system includes at least one of an impulse response of the clock recovery system and a frequency transfer function of the clock recovery system.

7. The measurement system of claim 1 wherein the response characteristic associated with the clock recovery system includes at least one of an impulse response of the clock recovery system and a frequency transfer function of the clock recovery system.

8. The measurement system of claim 3 wherein the ADC measures the phase error signal in the signal path, time-referenced to a trigger signal applied to the measurement module, with the input signal applied to the phase detector at an input to the PLL and the recovered clock signal applied to the phase detector from a feedback path of the PLL.

9. The measurement system of claim 8 wherein the trigger signal is derived from a modulating signal that modulates the input signal.

10. The measurement system of claim 9 wherein the response characteristic associated with the clock recovery system includes at least one of an impulse response of the clock recovery system and a frequency transfer function of the clock recovery system.

11. The measurement system of claim 10 wherein the processor deconvolves the measured phase error signal with the impulse response of the clock recovery system when the response characteristic associated with the clock recovery system is the impulse response of the clock recovery system.

12. The measurement system of claim 10 wherein the processor determines an inverse Fourier Transform of the ratio of a Fourier Transform of the measured phase error signal to the frequency transfer function when the response characteristic associated with the clock recovery system is the frequency transfer function of the clock recovery system.

13. The measurement system of claim 8 wherein the ADC measures the phase error signal by acquiring multiple sets of samples of the phase error signal and averaging the samples in each of the multiple sets of samples that have corresponding indices.

14. A measurement system, comprising:

a clock recovery system having an associated response characteristic, receiving an input signal and recovering a clock signal from the input signal;

a measurement module coupled to the clock recovery system, measuring a phase error signal time-referenced to a trigger signal applied to the measurement module, where the phase error signal is received from the clock recovery system and represents a phase difference between the input signal and the recovered clock signal; and

a processor applying the associated response characteristic to the measured phase error signal to determine the phase of the input signal.

15. The measurement system of claim 14 wherein measuring the phase error signal time-referenced to the trigger signal includes acquiring at least one set of samples of the phase error signal with an analog-to-digital converter (ADC) included in the measurement module.

16. The measurement system of claim 14 wherein measuring the phase error signal includes acquiring multiple sets of samples of the phase error signal with an analog-to-digital converter (ADC) included in the measurement module, and averaging the samples in each of the multiple sets of samples that have corresponding indices.

17. The measurement system of claim 14 wherein applying the associated response characteristic to the measured phase error signal to determine the phase of the input signal includes deconvolving the measured phase error signal with an impulse response of the clock recovery system when the response characteristic associated with the clock recovery system is the impulse response of the clock recovery system.

18. The measurement system of claim 17 wherein the impulse response is derived from a step response of the clock recovery system.

19. The measurement system of claim 14 wherein the response characteristic associated with the clock recovery system is a frequency transfer function of the clock recovery system, and wherein applying the associated response characteristic to the measured phase error signal to determine the phase of the input signal includes determining an inverse Fourier Transform of the ratio of a Fourier Transform of the measured phase error signal to the frequency transfer function.

20. The measurement system of claim 14 wherein the associated response characteristic of the clock recovery system is determined by selectively injecting a stimulus signal into a signal summer interposed between a phase detector and a loop integrator of a phase-locked loop (PLL) within the clock recovery system, with a data signal applied to a first input of the phase detector and with the PLL in a phase locked state, by measuring a calibration error signal in a signal path of the PLL between the signal summer and the loop integrator when the stimulus signal is injected into the signal summer, and by processing the measured calibration error signal to determine the associated response characteristic of the clock recovery system.