Memory block testing

• US 20070266276A1
• Filed: 04/12/2006
• Published: 11/15/2007
• Est. Priority Date: 04/12/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gajera, Nevil, Sinipete, Joemar, Gatzemeier, Scott, Hawes, Mark
• Granted Patent: US 7,567,472 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is less than or equal to a first predetermined time, and failing the memory block if the total programming time for the memory block exceeds the first predetermined time or the programming time for any one of the pages exceeds a second predetermined time.

Claims

1. A method of testing a memory device, comprising:

programming a plurality of pages of a memory block;

determining a programming time for each page;

determining a total programming time for the memory block;

passing the memory block if the total programming time for the memory block is less than or equal to a first predetermined time; and

failing the memory block if the total programming time for the memory block exceeds the predetermined first time or the programming time for any one of the pages exceeds a second predetermined time.

2. The method of claim 1, wherein determining a programming time for each page is based on a number of programming cycles required to program each page.

3. The method of claim 1, wherein determining a total programming time for the memory block is based on a total number of programming cycles required to program the memory block.

4. The method of claim 1, wherein passing the memory block comprises allowing a first number of pages to be programmed in a first programming time and at least a second number of pages to be programmed in a second programming time that is greater that the first programming time.

5. The method of claim 4, wherein passing the memory block further comprises allowing a third number of pages to be programmed in a third programming time that is greater than the second programming time.

6. The method of claim 5, wherein the first number of pages programmed in the first programming time, the second number of pages programmed in the second programming time, and the third number of pages programmed in the third programming time are selected so that the total programming time for the memory block is less than or equal to the first predetermined time.

7. A method of testing a memory device, comprising:

programming a plurality of pages of a memory block;

determining a programming time for each page;

passing the memory block if a first number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a second number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number; and

failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the first number of pages is less than the first predetermined number or if the second number of pages exceeds the second predetermined number.

8. The method of claim 7, wherein determining a programming time for each page is based on a number of programming pulses required to program that page.

9. The method of claim 7, wherein passing the memory block comprises allowing a third number of pages, each programmed at a third programming time that is greater than the first programming time and less than the second programming time.

10. The method of claim 9, wherein the third number of pages is greater than the second number of pages and less than the first number of pages.

11. A method of testing a NAND memory device, comprising:

programming a plurality of pages of a memory block;

determining a number of pages programmed in a first predetermined programming time;

determining a number of pages programmed in a second predetermined programming time;

determining a number of pages programmed in a third predetermined programming time;

passing the memory block if the number of pages programmed in the first predetermined programming time is greater than or equal to a first predetermined number and the number of pages programmed in the third predetermined programming time is less than or equal to a second predetermined number; and

failing the memory block if a programming time of any one of the pages exceeds the third predetermined programming time or if the number of pages programmed in the first predetermined programming time is less than the first predetermined number or if the number of pages programmed in the third predetermined programming time exceeds the second predetermined number.

12. A method of testing a NAND memory device, comprising:

programming a plurality of pages of a memory block;

determining a number of pages programmed by a first number of programming pulses;

determining a number of pages programmed by a second number of programming pulses;

determining a number of pages programmed by a third number of programming pulses;

passing the memory block if the number of pages programmed by the first number of programming pulses is greater than or equal to a first predetermined number and the number of pages programmed by the third number of programming pulses is less than or equal to a second predetermined number; and

failing the memory block if any one of the pages requires more than the third number of programming pulses to be programmed or if the number of pages programmed by the first number of programming pulses is less than the first predetermined number or if the number of pages programmed by the third number of programming pulses exceeds the second predetermined number.

13. The method of claim 12, wherein each programming pulse has a duration of about 75 to about 100 microseconds.

14. The method of claim 13, wherein each programming pulse has a duration of about 77 to about 95 microseconds.

15. The method of claim 12, wherein the second number of programming pulses comprises one more programming pulse than the first number of programming pulses.

16. The method of claim 15, wherein the third number of programming pulses comprises one more programming pulse than the second number of programming pulses.

17. An electronic system, comprising:

a processor; and

one or more memory devices coupled to the processor, each of the one or more memory devices comprising a plurality of memory blocks, wherein the processor is adapted to perform a method of testing each memory block, the method comprising;

programming a plurality of pages of the memory block;

determining a programming time for each page;

determining a total programming time for the memory block;

passing the memory block if the total programming time for the memory block is less than or equal to a first predetermined time; and

failing the memory block if the total programming time for the memory block exceeds the predetermined first time or the programming time for any one of the pages exceeds a second predetermined time.

18. The electronic system of claim 17, wherein, in the method, determining a programming time for each page is based on a number of programming cycles required to program each page.

19. The electronic system of claim 17, wherein, in the method, determining a total programming time for the memory block is based on a total number of programming cycles required to program the memory block.

20. The electronic system of claim 17, wherein, in the method, passing the memory block comprises allowing a first number of pages to be programmed in a first programming time and at least a second number of pages to be programmed in a second programming time that is greater that the first programming time.

21. The electronic system of claim 20, wherein, in the method, passing the memory block further comprises allowing a third number of pages to be programmed in a third programming time that is greater than the second programming time.

22. The electronic system of claim 21, wherein, in the method, the first number of pages programmed in the first programming time, the second number of pages programmed in the second programming time, and the third number of pages programmed in the third programming time are selected so that the total programming time for the memory block is less than or equal to the first predetermined time.

23. The electronic system of claim 17, wherein the processor is a part of a testing system or tester hardware.

24. The electronic system of claim 17, wherein the method is performed in response to the processor receiving computer-readable instructions stored on a computer-usable media.

25. The electronic system of claim 24, wherein computer-usable media is selected from the group consisting of hardware, software, and firmware.

26. An electronic system, comprising:

a processor; and

one or more memory devices coupled to the processor, each of the one or more memory devices comprising a plurality of memory blocks, wherein the processor is adapted to perform a method of testing each memory block, the method comprising;

programming a plurality of pages of the memory block;

determining a programming time for each page;

passing the memory block if a first number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a second number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number; and

failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the first number of pages is less than the first predetermined number or if the second number of pages exceeds the second predetermined number.

27. The electronic system of claim 26, wherein, in the method, determining a programming time for each page is based on a number of programming pulses required to program that page.

28. The electronic system of claim 26, wherein, in the method, passing the memory block comprises allowing a third number of pages, each programmed at a third programming time that is greater than the first programming time and less than the second programming time.

29. The electronic system of claim 28, wherein, in the method, the third number of pages is greater than the second number of pages and less than the first number of pages.

30. The electronic system of claim 26, wherein the processor is a part of a testing system or tester hardware.

31. The electronic system of claim 26, wherein the method is performed in response to the processor receiving computer-readable instructions stored on a computer-usable media.

32. The electronic system of claim 31, wherein computer-usable media is selected from the group consisting of hardware, software, and firmware.

33. An electronic system, comprising:

a processor; and

one or more NAND memory devices coupled to the processor, each of the one or more NAND memory devices comprising a plurality of memory blocks, wherein the processor is adapted to perform a method of testing each memory block, the method comprising;

programming a plurality of pages of the memory block;

determining a number of pages programmed in a first predetermined programming time;

determining a number of pages programmed in a second predetermined programming time;

determining a number of pages programmed in a third predetermined programming time;

passing the memory block if the number of pages programmed in the first predetermined programming time is greater than or equal to a first predetermined number and the number of pages programmed in the third predetermined programming time is less than or equal to a second predetermined number; and

failing the memory block if a programming time of any one of the pages exceeds the third predetermined programming time or if the number of pages programmed in the first predetermined programming time is less than the first predetermined number or if the number of pages programmed in the third predetermined programming time exceeds the second predetermined number.

34. The electronic system of claim 33,- wherein the processor is a part of a testing system or tester hardware.

35. The electronic system of claim 33, wherein the method is performed in response to the processor receiving computer-readable instructions stored on a computer-usable media.

36. The electronic system of claim 35, wherein computer-usable media is selected from the group consisting of hardware, software, and firmware.

37. An electronic system, comprising:

a processor; and

one or more NAND memory devices coupled to the processor, each of the one or more NAND memory devices comprising a plurality of memory blocks, wherein the processor is adapted to perform a method of testing each memory block, the method comprising;

programming a plurality of pages of the memory block;

determining a number of pages programmed by a first number of programming pulses;

determining a number of pages programmed by a second number of programming pulses;

determining a number of pages programmed by a third number of programming pulses;

passing the memory block if the number of pages programmed by the first number of programming pulses is greater than or equal to a first predetermined number and the number of pages programmed by the third number of programming pulses is less than or equal to a second predetermined number; and

failing the memory block if any one of the pages requires more than the third number of programming pulses to be programmed or if the number of pages programmed by the first number of programming pulses is less than the first predetermined number or if the number of pages programmed by the third number of programming pulses exceeds the second predetermined number.

38. The electronic system of claim 37, wherein, in the method, each programming pulse has a duration of about 75 to about 100 microseconds.

39. The electronic system of claim 38, wherein, in the method, each programming pulse has a duration of about 77 to about 95 microseconds.

40. The electronic system of claim 37, wherein, in the method, the second number of programming pulses comprises one more programming pulse than the first number of programming pulses.

41. The electronic system of claim 40, wherein, in the method, the third number of programming pulses comprises one more programming pulse than the second number of programming pulses.

42. The electronic system of claim 37, wherein the processor is a part of a testing system or tester hardware.

43. The electronic system of claim 37, wherein the method is performed in response to the processor receiving computer-readable instructions stored on a computer-usable media.

44. The electronic system of claim 43, wherein computer-usable media is selected from the group consisting of hardware, software, and firmware.