Data Plane Technology Including Packet Processing for Network Processors

• US 20070266370A1
• Filed: 09/16/2005
• Published: 11/15/2007
• Est. Priority Date: 09/16/2004
• Status: Abandoned Application

• Current Assignee: IP Fabrics Incorporated (ATIS UHER SA)
• Original Assignee: IP Fabrics Incorporated (ATIS UHER SA)
• Inventors: Schwaderer, Curtis, Imel, Michael, Graves, Kevin, Cassing, David, Myers, Glenford
• Application Number:
  US11/575,217
• Publication Number:
  US 20070266370A1
• Time in Patent Office: Days
• US Class Current: 717/119
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: H04L 45/586 of virtual routers
• CPC Class Codes: H04L 49/1523 Parallel switch fabric planes
• CPC Class Codes: H04L 49/3063 Pipelined operation

Abstract

The present invention provides methods and apparatus for abstracting network processors using a virtual machine. The virtual machine approach substantially abstracts the network processor, letting the application developer focus all attention on packet processing. In accordance with the present invention, the NPU-based virtual machine provides the functionality of a pipelined engine, N-way parallelism, or both. The present invention provides a high-level functional language for expressing a wide variety of packet processing applications. The high-level functional language provides primitives in the form of instructions such as, but not limited to, tracking a connection or session, removing an outer header, translating an IP address, encrypting a packet, and scanning the payload for a regular expression.

Claims

1. A packet processor for processing packet data, comprising:

a network processing unit; and

a virtual machine associated with the network processing unit, the virtual machine adapted to interpret packet processing bytecode into binary code readable by the network processing unit.

2. The packet processor of claim 1, wherein the network processing unit comprises a plurality of parallel processors, the virtual machine adapted for the parallel processing of packet processing bytecode enabling the network processing unit to parallel process the packet data.

3. The packet processor of claim 2, wherein the packet processing bytecode comprises:

policies comprising one or more packet processing functions;

rules comprising one or more expressions and actions adapted to apply the policies; and

events comprising one or more rules.

4. The packet processor of claim 3, wherein the virtual machine is adapted such that a plurality of rules are executed concurrently across a plurality of parallel processors of the network processing unit.

5. The packet processor of claim 4, wherein the virtual machine is adapted such that the events are dynamically assigned to respective processors.

6. The packet processor of claim 5, wherein the virtual machine is adapted such that the actions of true rules in an event are processed sequentially.

7. The packet processor of claim 5, wherein the virtual machine is adapted such that multiple instances of the same event are processed concurrently.

8. The packet processor of claim 5, further comprising:

a hardware accelerator associated with the virtual machine, the hardware accelerator adapted to implement at least part of a virtual machine.

9. The packet processor of claim 8, wherein the hardware accelerator comprises a packet content inspection co-processor adapted to reduce the number of rules.

10. The packet processor of claim 8, wherein the hardware accelerator is external of the network processing unit.

11. A method using pipelined and superscalar parallelism for a packet processing virtual machine, comprising:

providing a virtual machine adapted for association with a network processing unit, the virtual machine adapted to interpret packet processing bytecode into binary code readable by the network processing unit, wherein the packet processing bytecode comprises;

policies comprising one or more packet processing functions;

rules comprising one or more expressions and actions adapted to apply the policies; and

events comprising one or more rules; and

executing a plurality of rules concurrently across a plurality of parallel processors of the network processing unit.

12. The method of claim 11, further comprising:

dynamically assigning the events to respective processors.

13. The method of claim 12, further comprising:

executing the actions of true rules in an event sequentially.

14. The method of claim 13, further comprising:

executing multiple instances of the same event concurrently.

15. A method of using a virtual machine on parallel processors of a network processing unit for processing IP packets, comprising:

providing a virtual machine adapted for association with a network processing unit, the virtual machine adapted to interpret packet processing bytecode into binary code readable by the network processing unit, wherein the packet processing bytecode comprises;

policies comprising one or more packet processing functions;

rules comprising one or more expressions and actions adapted to apply the policies; and

events comprising one or more rules; and

executing a plurality of rules concurrently across the parallel processors of the network processing unit.

16. The method of claim 15, further comprising:

dynamically assigning the events to respective processors.

17. The method of claim 16, further comprising:

executing the actions of true rules in an event sequentially.

18. The method of claim 17, further comprising:

executing multiple instances of the same event concurrently.

19. A method for programming a network processing unit for packet processing using a virtual machine, comprising:

creating a bytecode using a packet processing language adapted for creating bytecode readable by a compiler;

compiling the bytecode written in packet processing language into binary code readable by the virtual machine; and

loading the binary code onto the virtual machine associated with the network processing unit.

20. The method of claim 19, wherein creating a bytecode using a packet processing language adapted for creating bytecode readable by a compiler comprises creating a bytecode using a packet processing language adapted for creating bytecode readable by a compiler, the packet processing language comprising:

policies comprising one or more packet processing functions;

rules comprising one or more expressions and actions adapted to apply the policies; and

events comprising one or more rules.