MULTITHREADED COMPUTER SYSTEM AND MULTITHREAD EXECUTION CONTROL METHOD

• US 20070266387A1
• Filed: 04/26/2007
• Published: 11/15/2007
• Est. Priority Date: 04/27/2006
• Status: Active Grant

• Current Assignee: Beijing Eswin Computing Technology Company Limited
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: HENMI, Masanori
• Granted Patent: US 8,001,549 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multithreaded computer system of the present invention includes a plurality of processor elements (PEs) 101 to 103, and a parallel processor control unit 200, which switches threads in each PE, and the parallel processor control unit 200 includes: a plurality of execution order registers, which hold, for each processor element, an execution order of threads to be executed; a plurality of counters 230, which count an execution time for a thread that is being executed by each processor element and generate a timeout signal when the counted time reaches a limit assigned to the thread; and a thread execution scheduler unit 210, which switches the thread that is being executed to the thread to be executed by each processor element based on the execution order held in said execution order register and the timeout signal.

Claims

1. A multithreaded computer system, comprising:

a plurality of processor elements, each of which is operable to execute a process including a plurality of threads; and

a control unit operable to switch threads to be executed in each processor element,

wherein said control unit includes;

a plurality of execution order registers, each of which is provided for a corresponding one of said processor elements, and which holds an execution order of threads to be executed by said corresponding processor elements;

a plurality of counters, each of which is provided for a corresponding one of said processor elements, each counter counting an execution time period for a thread that is being executed by said corresponding processor element and generating a timeout signal when the counted time reaches a limit assigned to the thread; and

a scheduling circuit operable to switch the thread that is being executed to the thread to be executed by each processor element based on the execution order held in said execution order register and the timeout signal.

2. The multithreaded computer system according to claim 1, wherein before execution of the plurality of threads starts, the execution order is written into one of said plurality of execution order registers by said corresponding processor element.

3. The multithreaded computer system according to claim 2, wherein said control unit further includes a mode register which holds mode information indicating either a single thread mode for disabling said scheduling circuit or a multithread mode for enabling said scheduling circuit, and said mode register is writable by said processor element.

4. The multithreaded computer system according to claim 3,

wherein said control unit further includes a plurality of priority level registers each of which is provided for a corresponding one of said processor elements, which holds priority level information indicating a thread that is to be preferentially executed in accordance with an interrupt signal to said processor element, and

when another interrupt signal is externally inputted, said scheduling circuit switches the thread to a thread corresponding to the interrupt signal.

5. The multithreaded computer system according to claim 3,

wherein each of said processor elements includes two context register groups which hold a context for a thread that is being executed and a context for a thread that is to be executed next,

said scheduling circuit further includes a context transfer unit operable to transfer context to save and restore contexts for said processor elements,

said scheduling circuit switches said context register groups at the time of thread switching, and

said context transfer unit transfers the context after the thread switching.

6. The multithreaded computer system according to claim 1,

wherein said control unit further includes:

a status register indicating whether each processor element is in an execution state or in a stopped state; and

a plurality of possibility information holding units provided corresponding to said processor elements, each possibility information holding unit holding possibility information as to whether parallel thread execution is possible, and

when any of said processor elements has transitioned from the execution state to the stopped state, said scheduling circuit further determines a thread available for parallel execution from among threads for other processor elements based on the possibility information, and causes said processor element in the stopped state to execute the determined thread.

7. The multithreaded computer system according to claim 6,

wherein the possibility information includes first information indicating whether or not parallel execution with another thread in the same process is possible and second information indicating whether or not execution by another processor element is possible, and

each of said possibility information holding units includes:

a first register which holds the first information; and

a second register which holds the second information.

8. The multithreaded computer system according to claim 7,

wherein before the execution of the threads starts, the execution order, the first information and the second information are respectively set in said execution order register, said first register and said second register by the corresponding processor element.

9. The multithreaded computer system according to claim 6,

wherein said control unit further includes a mode register operable to hold mode information indicating either a single thread mode for disabling said scheduling circuit or a multithread mode for enabling said scheduling circuit, and said mode register is writable by said processor element.

10. The multithreaded computer system according to claim 6,

wherein said control unit further includes a plurality of priority level registers provided corresponding to their respective processor elements, each priority level register holding priority level information indicating a thread that is to be preferentially executed in accordance with an interrupt signal to the corresponding processor element, and

when another interrupt signal is externally inputted, said scheduling circuit switches the thread to a thread in accordance with that interrupt signal.

11. The multithreaded computer system according to claim 6,

wherein each of said processor elements includes two context register groups holding a context for a thread that is being executed and a context for a thread that is to be executed next,

said scheduling circuit further includes a context transfer unit operable to perform context transfer to save and restore contexts for said processor elements,

said scheduling circuit switches said context register groups at the time of thread switching, and

said context transfer unit performs the context transfer after the thread switching.

12. The multithreaded computer system according to claim 6, further comprising a clock control unit operable to suppress a clock signal from being supplied to any processor element in the stopped state.

13. The multithreaded computer system according to claim 12,

wherein said control unit further includes a clock control register which holds clock control information indicating whether or not clock supply should be suppressed, for each processor element, and

said control unit enables or disables said clock control unit for each processor element in accordance with the clock control information.

14. A multithread execution control method for use in a multithreaded computer system including:

a plurality of processor elements operable to execute a process including a plurality of threads; and

a control unit operable to switch threads to be executed in each processor element,

wherein said control unit includes;

a plurality of execution order registers provided corresponding to their respective processor elements, each execution order register holding an execution order of threads to be executed in the corresponding processor element;

a plurality of counters provided corresponding to their respective processor elements, each counter counting an execution time for a thread being executed by the corresponding processor element and generating a timeout signal when the counted time reaches a limit assigned to the thread; and

a scheduling circuit operable to switch the thread that is being executed to the thread to be executed by each processor element based on the execution order held in said execution order register and the timeout signal, and

said multithread execution control method comprises;

setting the execution order in said execution order register when said corresponding processor element is in a single thread mode;

setting said processor element in a multithread mode; and

executing a thread in said processor element in the multithread mode, while performing thread switching.