Apparatus and Method for Test Structure Inspection

• US 20070267632A1
• Filed: 01/03/2007
• Published: 11/22/2007
• Est. Priority Date: 01/03/2006
• Status: Active Grant

• Current Assignee: Applied Materials Israel Limited (Applied Materials Incorporated)
• Original Assignee: Applied Materials Israel Limited (Applied Materials Incorporated)
• Inventors: Bullock, Eugene
• Granted Patent: US 7,902,849 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/305 using electron beams investigating or analysing materials by measuring photoelectric effect G01N23/227
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Abstract

Herein are described layouts of test structures and scanning methodologies that allow large probe currents to be used so as to allow the detection of resistive defects with a resistance lower than 1 MΩ while at the same time allowing a sufficient degree of localization to be obtained for root cause failure analysis. The detection of resistances lower than 1 MΩ nominally requires a probe current greater than 1 micro ampere for detection on an electron beam inspection system.

Claims

1. A method for forming a semiconductor die, the method comprising:

providing a first test structure having a first end and a second end, wherein the first end of the first test structure is electrically coupled to a conducting pad; and

with a probe, injecting a current into the first test structure at the conducting pad so as to saturate the conductance of the first test structure and detect resistive defects at a low level of resistance within a portion of the first test structure associated with the conductance pad.

2. The method of claim 1, wherein the first end of the first test structure is floating, and the second end of the first test structure is electrically coupled to a wafer on which said semiconductor die is disposed.

3. The method of claim 1, wherein the first end and the second end of the first test structure are floating, and the second end of the first test structure is electrically coupled to a large capacitance.

4. The method of claim 1, wherein the first test structure is a contact or via chain system.

5. The method of claim 1, wherein the first test structure is formed in a double serpentine pattern.

6. The method of claim 1, wherein the first test structure is positioned in relation to a second test structure so as to allow testing of both the first and second test structures.

7. The method of claim 6, wherein the first and second test structures form a comb structure for testing shorts between adjacent metal lines.

8. The method of claim 1, wherein injecting a current into the first test structure at the conducting pad includes moving the semiconductor die or the beam in relation to one another so as to sequentially scan a plurality of test structures arranged on the semiconductor die sequentially along a direction of a stage axis.

9. The method of claim 1, wherein injecting a current into the first test structure at the conducting pad includes moving the semiconductor die or the beam in relation to one another so as to sequentially scan a plurality of test structures arranged on the semiconductor die sequentially in a mirror format along a direction of a stage axis.

10. A semiconductor die, comprising:

a first test structure having a first end and a second end, wherein the first end of the first test structure is electrically coupled to a conducting pad providing an injection point for receiving a current into the first test structure so as to saturate the conductance of the first test structure and detect resistive defects at a low level of resistance within a portion of the first test structure associated with the conductance pad.

11. The semiconductor die of claim 10, wherein the first end of the first test structure is floating, and the second end of the first test structure is electrically coupled to a wafer on which said semiconductor die is disposed.

12. The semiconductor die of claim 10, wherein the first end and the second end of the first test structure are floating, and the second end of the first test structure is electrically coupled to a large capacitance.

13. The semiconductor die of claim 10, wherein the first test structure is a contact or via chain system.

14. The semiconductor die of claim 10, wherein the first test structure is formed in a double serpentine pattern.

15. The semiconductor die of claim 10, wherein the first test structure is positioned in relation to a second test structure so as to allow testing of both the first and second test structures.

16. The semiconductor die of claim 15, wherein the first and second test structures form a comb structure for testing shorts between adjacent metal lines.

17. The semiconductor die of claim 10, further comprising:

in addition to the first test structure, a plurality of test structures arranged on the semiconductor die sequentially along a direction of a stage axis to enable a current to be injected into a conducting pad by moving the semiconductor die or the beam in relation to one another along the direction of the stage axis.

18. The semiconductor die of claim 10, further comprising:

in addition to the first test structure, a plurality of test structures arranged on the semiconductor die sequentially in a mirror format along a direction of a stage axis to enable a current to be injected into a conducting pad by moving the semiconductor die or the beam in relation to one another along the direction of the stage axis.