SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20070267672A1
• Filed: 05/04/2007
• Published: 11/22/2007
• Est. Priority Date: 05/18/2006
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takano, Akio, HOKOMOTO, Yoshitaka, Katoh, Shunsuke
• Application Number:
  US11/744,344
• Publication Number:
  US 20070267672A1
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a plurality of first trenches passing through the second semiconductor layer and reaching the first semiconductor layer; a gate insulating film provided on an inner wall of the first trench; and a gate electrode filling in the first trench via the gate insulating film. A PN junction interface is provided between the first semiconductor layer and the second semiconductor layer. A distance from an upper face of the second semiconductor layer to the PN junction interface is minimized nearly at a center between the first trenches.

Claims

1. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;

a plurality of first trenches passing through the second semiconductor layer and reaching the first semiconductor layer;

a gate insulating film provided on an inner wall of the first trench; and

a gate electrode filling in the first trench via the gate insulating film,

a PN junction interface being provided between the first semiconductor layer and the second semiconductor layer, and

a distance from an upper face of the second semiconductor layer to the PN junction interface being minimized nearly at a center between the first trenches.

2. The semiconductor device according to claim 1, further comprising:

a second trench provided between the adjacent first trenches; and

a contact region of the second conductivity type provided at a bottom of the second trench and electrically connected to the second semiconductor layer.

3. The semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer include at least one selected from the group consisting of Si, GaAs, SiC, GaN, SiGe, and C.

4. The semiconductor device according to claim 1, wherein the gate insulating film includes at least one selected from the group consisting of a silicon oxide film, a laminated film of silicon nitride film and silicon oxide film, a film having a dielectric constant higher than silicon oxide, an oxynitride film, and an insulating film made by any combination thereof.

5. The semiconductor device according to claim 1, further comprising:

a third semiconductor layer of the second conductivity type provided on a surface of the first semiconductor layer, the surface being opposite to a surface on which the second semiconductor layer is provided.

6. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;

a plurality of first trenches passing through the second semiconductor layer and reaching the first semiconductor layer;

a gate insulating film provided on an inner wall of the first trench;

a gate electrode filling in the first trench via the gate insulating film;

a plurality of first diffusion regions of the first conductivity type selectively provided in the upper surface of the second semiconductor layer; and

a contact region of the second conductivity type provided between the first diffusion regions in the second semiconductor layer,

a PN junction interface being provided between the first semiconductor layer and the second semiconductor layer, and

the PN junction interface having a protruding feature at a position corresponding to the contact region.

7. The semiconductor device according to claim 6, wherein the first semiconductor layer and the second semiconductor layer include at least one selected from the group consisting of Si, GaAs, SiC, GaN, SiGe, and C.

8. The semiconductor device according to claim 6, wherein the gate insulating film includes at least one selected from the group consisting of a silicon oxide film, a laminated film of silicon nitride film and silicon oxide film, a film having a dielectric constant higher than silicon oxide, an oxynitride film, and an insulating film made by any combination thereof.

9. The semiconductor device according to claim 6, further comprising:

a third semiconductor layer of the second conductivity type provided on a surface of the first semiconductor layer, the surface being opposite to a surface on which the second semiconductor layer is provided.

10. A method for manufacturing a semiconductor device comprising:

forming a first insulating film on an upper face of a first semiconductor crystal layer of a first conductivity type;

forming a plurality of first openings in the first insulating film and then partially removing the first semiconductor crystal layer exposed in the first openings to form a plurality of first trenches;

setting back the first insulating film having the first openings to form a second insulating film and to expose an upper corner of the first trench;

forming a gate insulating film on an inner wall of the first trench;

filling in the first trench with a gate electrode material via the gate insulating film;

introducing a first dopant of a second conductivity type and a second dopant of the first conductivity type into the corner and the gate electrode material, respectively, by ion implantation from above the first semiconductor crystal layer using the second insulating film as a mask; and

thermally diffusing the first dopant and the second dopant introduced into the corner and the gate electrode material to convert the gate electrode material into a conductor of the first conductivity type, to form a second semiconductor layer of the second conductivity type in the first semiconductor crystal layer, and to form a diffusion region of the first conductivity type in the corner.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising:

forming an interlayer insulating film so as to overlie the first trench, the corner, and the second insulating film;

forming a second opening in a portion of the interlayer insulating film, the portion corresponding to above a position between the adjacent first trenches, and then partially removing the first semiconductor crystal layer exposed in the second opening to form a second trench; and

forming a contact region of the second conductivity type electrically connected to the second semiconductor layer by ion implantation of the second conductivity type using the interlayer insulating film having the second opening as a mask.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the first semiconductor layer and the second semiconductor layer include at least one selected from the group consisting of Si, GaAs, SiC, GaN, SiGe, and C.

13. The method for manufacturing a semiconductor device according to claim 10, wherein the gate insulating film includes at least one selected from the group consisting of a silicon oxide film, a laminated film of silicon nitride film and silicon oxide film, a film having a dielectric constant higher than silicon oxide, an oxynitride film, and an insulating film made by any combination thereof.

14. The method for manufacturing a semiconductor device according to claim 10, wherein the first semiconductor crystal layer includes Si, and the first and second dopant are boron and arsenic, respectively.

15. The method for manufacturing a semiconductor device according to claim 10, wherein the step of setting back the first insulating film uses isotropic etching.