Non-volatile memory error correction system and method

• US 20070268905A1
• Filed: 05/18/2006
• Published: 11/22/2007
• Est. Priority Date: 05/18/2006
• Status: Abandoned Application

• Current Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: Sanders, Richard, Baker, David Cureton
• Application Number:
  US11/436,937
• Publication Number:
  US 20070268905A1
• Time in Patent Office: Days
• US Class Current: 370/392
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

A non-volatile memory has a first payload data region and a first redundant memory area associated with the first payload data region. The first redundant memory area has a first portion, a second portion and a third portion. The first portion includes first payload error correction code (ECC) data associated with the first payload data region. The second portion includes first metadata associated with the first payload data region. The third portion includes first metadata ECC data associated with the first metadata.

Claims

1. A non-volatile memory comprising:

a first payload data region;

a first redundant memory area associated with the first payload data region, the first redundant memory area comprising;

a first portion including first payload error correction code (ECC) data associated with the first payload data region;

a second portion including first metadata associated with the first payload data region; and

a third portion including first metadata ECC data associated with the first metadata.

2. The non-volatile memory of claim 1, further comprising:

a second payload data region; and

wherein the first metadata is associated with the first payload data region and the second payload data region.

3. The non-volatile memory of claim 2, wherein the first redundant memory area includes second payload error correction code (ECC) data associated with the second payload data region.

4. The non-volatile memory of claim 1, wherein the first payload error correction code (ECC) data includes parity data and syndrome data.

5. The non-volatile memory of claim 1, wherein the first payload data region comprises a memory space of 512 bytes.

6. The non-volatile memory of claim 1, wherein the first metadata includes cyclic redundancy check (CRC) data.

7. The non-volatile memory of claim 1, wherein the first metadata includes block status data.

8. The non-volatile memory of claim 1, wherein the first metadata includes logical address data associated with the first payload data region.

9. The non-volatile memory of claim 1, further comprising:

a second payload region;

a second redundant memory area associated with the second payload data region, the second redundant memory area comprising;

a first portion having second payload error correction code (ECC) data associated with the second payload region;

a second portion having second metadata associated with the second payload region; and

a third portion including second metadata ECC data associated with the second metadata.

10. A system comprising:

a non-volatile memory including payload error correction code (ECC) data associated with a payload data region and metadata ECC data that is associated with the payload data region;

an error correction module including logic to perform error correction in response to receiving the metadata ECC data.

11. The system of claim 10, wherein the metadata ECC data includes an error syndrome, and wherein the error correction module includes a syndrome generation module to generate the error syndrome.

12. The system of claim 10, wherein the error correction module includes a key generation module to generate error correction information based on the error syndrome to correct an error in metadata accessed from the non-volatile memory.

13. The system of claim 12, wherein the error correction information includes an error index and an error mask.

14. The system of claim 10, wherein the non-volatile memory includes payload ECC data and metadata ECC data, each associated with a second payload data region.

15. The system of claim 12, wherein the error correction module performs Reed-Solomon error correction on the metadata.

16. A method comprising:

generating a data protection code related to a data payload;

generating a metadata protection code related to the data protection code; and

storing the data payload in a payload data region of a non-volatile memory and storing the data protection code and the metadata protection code in a redundant data region of the non-volatile memory.

17. The method of claim 16, wherein the data protection code comprises error detection data and error correction data.

18. The method of claim 17, wherein the error detection data comprises parity data.

19. The method of claim 16, wherein the data protection code comprises cyclic redundancy check (CRC) data and error correction code (ECC) data.

20. The method of claim 16, wherein the metadata protection code comprises error correction code (ECC) data related to the data protection code.

21. The method of claim 16, wherein generating the data protection code comprises calculating at least one parity data and error correction code (ECC) data for the data payload.

22. The method of claim 16, wherein generating the metadata protection code comprises calculating metadata error correction code (ECC) data.

23. A system comprising:

an error correction module having access to a non-volatile memory, the error correction module including logic to generate a plurality of syndromes associated with a block of data retrievable from the non-volatile memory, the error correction module further including logic to compensate for bit errors within the block of data and including logic to use metadata error correction code (ECC) data to correct for bit errors in metadata retrieved from the non-volatile memory.