SEMICONDUCTOR WAFER AND METHOD FOR MAKING THE SAME

• US 20070269961A1
• Filed: 05/22/2007
• Published: 11/22/2007
• Est. Priority Date: 03/22/2006
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wu, Ping-Chang
• Application Number:
  US11/752,268
• Publication Number:
  US 20070269961A1
• Time in Patent Office: Days
• US Class Current: 438/462
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT pads has thereon a slot opening. A reinforcement structure is formed within the slot opening and penetrates through the WAT pad for stopping propagation of de-lamination during wafer dicing.

Claims

1. A method of dicing a semiconductor wafer, comprising:

forcing a plurality of active circuit die areas on a semiconductor wafer, each of the active circuit die areas being bordered by a dicing line;

forming a plurality of pads in the dicing line;

forming a reinforcing structure in the pads and along at least one side of each said pad; and

dicing the semiconductor wafer along the dicing line.

2. The method according to claim 1 wherein the reinforcing structure comprises a plurality of vias in a plurality of dielectric layers.

3. The method according to claim 2 wherein the plurality of vias comprises at least one row of vias.

4. The method according to claim 2 wherein the plurality of vias comprises at least a via bar.

5. The method according to claim 2 wherein the plurality of vias have air gap therein.

6. The method according to claim 2 wherein the plurality of vias are filled with metal.

7. The method according to claim 6 wherein the metal comprises copper.

8. The method according to claim 1 wherein the reinforcing structure is disposed along two sides of each said pad in parallel with the dicing line.