Adaptable datapath for a digital processing system
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Abstract
The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., discrete cosine transform (DCT), fast-Fourier transform (FFT) and other operations. Other features are provided.
101 Citations
20 Claims
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1-5. -5. (canceled)
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6. A data path circuit in a digital processing device, wherein the data path circuit is coupled to a memory bus for obtaining values from a memory, the data path circuit comprising
a plurality of groups of data lines; -
a plurality of data address generators for coupling the plurality of groups of data lines to the memory bus so that a value from the memory transferred by the memory bus can be placed onto a group of data lines;
one or more functional units for performing a digital operation coupled to the plurality of groups of data lines; and
a plurality of register files, wherein each register file in the plurality of registers is coupled to a group of data lines in the plurality of data lines in a one-to-one correspondence, wherein each of the plurality of register files store values from the group of data lines in which each of the plurality of register files is coupled. - View Dependent Claims (7, 8, 9, 18, 19, 20)
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10. A digital processing system comprising
a multiplier; -
an accumulator;
a configurable data path coupled to both the multiplier and the accumulator in parallel; and
a direct data path coupled between the multiplier and the accumulator.
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11. A data path circuit in a digital processing device, wherein the data path circuit is coupled to a memory bus for obtaining values from a memory, the data path circuit comprising
a plurality of groups of data lines; -
a plurality of data address generators for coupling the plurality of groups of data lines to the memory bus so that a value from the memory transferred by the memory bus can be placed onto a group of data lines;
one or more functional units for performing a digital operation coupled to the plurality of groups of data lines; and
a plurality of register files, wherein each register file in the plurality of registers is coupled to a single group of data lines in the plurality of data lines, wherein each of the plurality of register files store values from the group of data lines in which each of the plurality of register files is coupled. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification