Memory module, a memory system including a memory controller and a memory module and methods thereof

• US 20070271424A1
• Filed: 03/22/2007
• Published: 11/22/2007
• Est. Priority Date: 05/16/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hoe-Ju, Lee, Jung-Bae
• Granted Patent: US 8,185,711 B2
• Time in Patent Office: Days
• US Class Current: 711/156
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation, transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit and writing the transferred write data at the at least one memory device. An example read operation may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal and an address from the received packet command if the received packet command corresponds to a read operation, transferring the extracted command signal and address to at least one memory device, receiving read data corresponding to the extracted command signal and address from the at least one memory device via write/read data lines internal to the given one memory unit and transmitting the received read data from the interface via read data lines external to the given one memory unit.

Claims

1. A memory module, comprising:

a plurality of memory units, each of the plurality of memory units including an interface receiving a packet command to generate a command signal and an address, extracting write data from the received packet command and transferring the extracted write data to memory during a write operation and receiving read data during a read operation and at least one memory device receiving the extracted write data during the write operation, and configured to output the read data during the read operation.

2. The memory module of claim 1, wherein the interface transfers the extracted write data via write/read data lines during the write operation, the interface receives the read data via the write/read data lines during the read operation and transmits the received read data via read data lines, the at least one memory device including at least two first memories, each of the at least two memories receiving the command signal and the address in common and outputting the read data via the write/read data lines during the read operation.

3. The memory module of claim 2, wherein the write/read data lines are connected to the interface and the at least two first memories in common, the write data includes of at least two groups of write data, the at least two groups of write data being sequentially output from the at least two first memories, the read data includes at least two groups of read data, the at least two groups of read data being sequentially output from the at least two first memories.

4. The memory module of claim 3, wherein if a first of the at least two first memories has a write latency of n, a read latency of m, a burst length of k and a clock period of j corresponding to the burst length, a second of the at least two first memories has a write latency of n+j, a read latency of m+j and a burst length of k.

5. The memory module of claim 2, wherein the write/read data lines include at least two groups of write/read data lines separately connected between the interface and each of the at least two first memories, the write data including at least two groups of write data, the at least two groups of write data concurrently transmitted to the at least two first memories, the read data including at least two groups of read data, the at least two groups of read data concurrently output from the at least two first memories, respectively.

6. The memory module of claim 5, wherein corresponding write latencies, read latencies, and burst lengths for each of the at least two first memories are the same.

7. The memory module of claim 2, wherein each of the memory units further includes:

at least two second memories receiving the command signal and the address in common, receiving the write data transmitted to the write/read data lines during the write operation, and transmitting the read data to the write/read data lines during the read operation.

8. The memory module of claim 7, wherein the packet command includes a first chip selection signal for enabling operations of the at least two first memories and a second chip selection signal for enabling operations of the at least two second memories.

9. The memory module of claim 8, wherein the write/read data lines include first write/read data lines connected between the interface and a first of the at least two first memories and a first of the at least two second memories in common, and second write/read data lines connected between the interface and a second of the at least two first memories and a second of the at least two second memories in common.

10. The memory module of claim 9, wherein if the first of the at least two first memories and the first of the at least two second memories have a write latency of n, a read latency of m, a burst length of k and a clock period of j corresponding to the burst length, the second of the at least two first memories and the second of the at least two second memories have a write latency of n+j, a read latency of m+j and a burst length of k.

11. The memory module of claim 7, wherein the write/read data lines are connected between the interface and the at least two first memories and the at least two second memories in common.

12. The memory module of claim 11, wherein corresponding write latencies, read latencies, and burst lengths of the at least two first memories and the at least two second memories, respectively, are the same.

13. The memory module of claim 2, wherein the interface receives the packet command transmitted at a first operating frequency and transfers the extracted write data included in the packet command at a second operating frequency during the write operation, and receives the read data at the second operating frequency from one or more of the at least two first memories and transmits the read data to the write/read data lines at the first operating frequency during the read operation, the first operating frequency being higher than the second operating frequency.

14. The memory module of claim 2, wherein the read data lines include pairs of differential data lines for transmitting differential data, and the write/read data lines include single data lines for transmitting single data.

15. A memory system, comprising:

the memory module of claim 2; and

a memory controller transmitting the packet command to the memory module via the write/read data lines, the transmitted packet command associated with one of a write operation and a read operation, the memory controller receiving the read data from the memory module via the read data lines during a read operation.

16. The memory module of claim 1, wherein the interface includes a first memory, the extracted write data including first write data and second write data, the interface storing the first write data in the first memory and transferring the second write data via write/read data lines during a write operation, the interface enabling the first memory to generate first read data, receiving second read data via the write/read data lines and outputting the first and second read data to read data lines during a read operation, the at least one memory device receiving the second write data via the write/read data lines during the write operation and transmitting the second read data via the write/read data lines during the read operation.

17. The memory module of claim 16, wherein the at least one memory device includes at least two second memories.

20. The memory module of claim 17, wherein the write/read data lines include at least two groups of write/read data lines separately connected between the interface and each of the at least two second memories.

21. The memory module of claim 20, wherein corresponding write latencies, read latencies, and burst lengths of each of the at least two second memories are the same.

22. The memory module of claim 16, wherein the interface receives the packet command transmitted at a first operating frequency and transfers the extracted write data included in the packet command at a second operating frequency during the write operation, the interface receiving the read data transmitted at the second operating frequency from the at least one memory device and transmitting the read data at the first operating frequency during the read operation via the read data lines, the first operating frequency being higher than the second operating frequency.

23. The memory module of claim 16, wherein the read data lines include pairs of differential data lines for transmitting differential data, and the write/read data lines include single data lines for transmitting single data.

24. A memory system, comprising:

the memory module of claim 16; and

a memory controller transmitting the packet command to the memory module via the write/read data lines, the transmitted packet command associated with one of a write operation and a read operation, the memory controller receiving the read data from the memory module via the read data lines during a read operation.

25. The memory module of claim 1, wherein the interface includes a first memory, the interface configured to either store the extracted write data in the first memory or transfer the extracted write data via write/read data lines during a write operation, the interface further configured to receive read data generated at the first memory or received via the write/read data lines and to output the received read data via read data lines during a read operation, the at least one memory device receiving the write data via the write/read data lines during the write operation, and transmitting the read data via the write/read data lines during the read operation.

26. The memory module of claim 25, wherein the at least one memory device includes at least two second memories.

27. The memory module of claim 26, wherein the write/read data lines are connected between the interface and the at least two second memories in common, the second write data include at least two groups of third write data, the at least two groups of third write data sequentially output to the at least two second memories during the write operation, the second read data including at least two groups of third read data, the at least two groups of third read data sequentially output from the at least two second memories during the read operation.

28. The memory module of claim 27, wherein if a first of the at least two second memories has a write latency of n, a read latency of m, a burst length of k and a clock period of j corresponding to the burst length, a second of the at least two second memories has a write latency of n+j, a read latency of m+j and a burst length of k.

29. The memory module of claim 26, wherein the write/read data lines include at least two groups of write/read data lines separately connected between the interface and each of the at least two second memories.

30. The memory module of claim 26, wherein corresponding write latencies, read latencies, and burst lengths of each of the at least two second memories are the same.

31. The memory module of claim 25, wherein the interface receives the packet command transmitted at a first operating frequency and transfers the extracted write data at a second operating frequency during the write operation, and the interface receives the read data at the second operating frequency from the memory device and transmits the read data at the first operating frequency during the read operation, the first operating frequency being higher than the second operating frequency.

32. The memory module of claim 25, wherein the read data lines include pairs of differential data lines for transmitting differential data, and the write/read data lines include single data lines for transmitting single data.

33. A memory system, comprising:

the memory module of claim 25; and

a memory controller transmitting the packet command to the memory module via the write/read data lines, the transmitted packet command associated with one of a write operation and a read operation, the memory controller receiving the read data from the memory module via the read data lines during a read operation.

34. The memory module of claim 1, wherein the interface is connected to the at least one memory via internal write/read data lines and the interface is connected to a memory controller at least via external read data lines.

35. The memory module of claim 34, wherein the internal write/read data lines are configured to transfer signals at lower speeds than the external read data lines.

36. The memory module of claim 34, wherein read data is reported to from the interface to the memory controller via the read data lines, and read and write data is exchanged between the interface and the at least one memory during read and write operations, respectively.

37. A memory system, comprising:

the memory module of claim 1; and

a memory controller transmitting the packet command to the memory module via the write/read data lines, the transmitted packet command associated with one of a write operation and a read operation, the memory controller receiving the read data from the memory module via the read data lines during a read operation.

18. The memory module of 17, wherein the write/read data lines are connected between the interface and the at least two second memories in common, the second write data includes at least two groups of third write data, the at least two groups of third write data sequentially output to the at least two second memories during the write operation, the second read data including at least two groups of third read data, the at least two groups of third read data sequentially output from the at least two second memories during the read operation.

19. The memory module of claim 18, wherein if a first of the at least two second memories has a write latency of n, a read latency of m, a burst length of k and a clock period of j corresponding to the burst length, a second of the at least two second memories has a write latency of n+j, a read latency of m+j and a burst length of k.

38. A method of performing a write operation, comprising:

receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device;

extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation;

transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit; and

writing the transferred write data at the at least one memory device.

39. A method of performing a read operation, comprising:

receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device;

extracting a command signal and an address from the received packet command if the received packet command corresponds to a read operation;

transferring the extracted command signal and address to at least one memory device;

receiving read data corresponding to the extracted command signal and address from the at least one memory device via write/read data lines internal to the given one memory unit; and

transmitting the received read data from the interface via read data lines external to the given one memory unit.

40. The method of claim 39, wherein the transmitting step transmits the received read data to a memory controller connected to the given one memory unit via the read data lines.

41. The method of claim 39, wherein the read data received via the internal write/read data lines is received at a lower speed than the read data is transmitted via the read data lines.