Availability of space in a RISC microprocessor architecture

• US 20070271441A1
• Filed: 07/26/2007
• Published: 11/22/2007
• Est. Priority Date: 10/06/1995
• Status: Abandoned Application

• Current Assignee: Bradley Jensen, Charles Moore, George Shaw, Martin Mcclurg, Russell Fish
• Original Assignee: Bradley Jensen, Charles Moore, George Shaw, Martin Mcclurg, Russell Fish
• Inventors: Jensen, Bradley, Fish, Russell, Shaw, George, Moore, Charles, McClurg, Martin
• Application Number:
  US11/881,283
• Publication Number:
  US 20070271441A1
• Time in Patent Office: Days
• US Class Current: 712/41
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/322 for non-sequential address
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

Claims

1. A microprocessor system, comprising:

a register unit, said register unit comprising at least one storage location containing a value to be interpreted as a memory address;

a memory interface unit coupled to said register unit;

a memory bus coupled to said memory interface unit; and

a system memory coupled to said memory interface unit by said memory bus, said memory interface unit comprising transfer logic to increment said memory address and to generate a boundary detected signal when, after a memory bus transaction to said system memory using said memory address, said memory address after incrementing has a value that is an even multiple of 2ⁿ, where n is a nonnegative integer.

2. The microprocessor system of claim 1, further comprising:

a microprocessing unit coupled to said memory interface unit and including means to interrupt said microprocessing unit after said boundary detected signal is generated by said memory interface unit.

3. The microprocessor system of claim 1, further comprising:

means coupled to said memory interface unit for generating a transfer request signal as an input to said memory interface unit for requesting said memory bus transaction to occur.

4. The microprocessor system of claim 3, further comprising:

an input-output processor (IOP) coupled to said memory interface unit, and said means for generating the transfer request signal is a means to execute instructions, one of said instructions activating said transfer request signal.

5. The microprocessor system of claim 1, wherein:

said incrementing of said memory address and the resulting said boundary detected signal is used to count an event.

6. The microprocessor system of claim 1, additionally comprising:

means coupled to said memory interface unit to disable said transfer logic to prevent further transfers after said boundary detected signal is generated.

7. The microprocessor system of claim 1, further comprising:

an input-output device coupled to said memory bus, wherein said memory address is further comprised of a first grouping of address bits used to address said system memory and a second group of address bits used to address said input-output device.

8. The microprocessor system of claim 1, further comprising:

a microprocessing unit (MPU), wherein said MPU is interrupted when said boundary detected signal is initiated.

9. The microprocessor system of claim 1, further comprising:

a direct memory access controller (DMAC), wherein said DMAC is terminated when said boundary detected signal is initiated

10. A method of avoiding overflow and underflow of a memory boundary in a microprocessor memory page, comprising:

accessing a boundary area of said memory page;

initiating a boundary detected signal upon said accessing; and

moving a stack pointer to a middle region of said memory page.

11. The method of claim 10, further comprising:

reallocating existing memory pages in order to accommodate said accessing a boundary area of said memory page.

12. The method of claim 10, wherein:

said boundary area comprises a region located 32 cells from the ends of each page.

13. The method of claim 10, wherein:

said accessing a boundary area consists of one of local stack overflow, local stack underflow, operand stack overflow, and operand stack underflow.

14. The method of claim 10, wherein:

said accessing a boundary area consists of one of stack spills and stack refills, which occurs between execution of instructions.

15. The method of claim 10, further comprising:

providing a microprocessing unit (MPU), wherein said MPU is interrupted when said boundary detected signal is initiated.

16. The method of claim 10, further comprising:

providing a direct memory access controller (DMAC), wherein said DMAC is terminated when said boundary detected signal is initiated.

17. The method of claim 10, further comprising:

providing a register unit, said register unit comprising at least one storage location containing a value to be interpreted as a memory address;

providing a memory interface unit coupled to said register unit; and

providing a memory bus coupled to said memory interface unit.

18. The method of claim 17, wherein:

said memory interface unit comprises transfer logic to increment said memory address and to generate said boundary detected signal.

19. The method of claim 18, wherein:

after said incrementing, said memory address has a value that is an even multiple of 2ⁿ where n is a nonnegative integer.

20. The method of claim 17, further comprising:

generating a transfer request signal as an input to said memory interface unit for requesting a memory bus transaction to occur.

21. The method of claim 18, wherein:

said incrementing of said memory address and the resulting said boundary detected signal is used to count an event.

22. The method of claim 18, further comprising:

disabling said transfer logic to prevent further transfers after said boundary detected signal is generated.

23. The method of claim 17, further comprising:

providing an input-output device coupled to said memory bus, wherein said memory address is further comprised of a first grouping of address bits used to address a system memory and a second group of address bits used to address said input-output device.