Availability of space in a RISC microprocessor architecture
First Claim
1. A microprocessor system, comprising:
- a register unit, said register unit comprising at least one storage location containing a value to be interpreted as a memory address;
a memory interface unit coupled to said register unit;
a memory bus coupled to said memory interface unit; and
a system memory coupled to said memory interface unit by said memory bus, said memory interface unit comprising transfer logic to increment said memory address and to generate a boundary detected signal when, after a memory bus transaction to said system memory using said memory address, said memory address after incrementing has a value that is an even multiple of 2n, where n is a nonnegative integer.
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Abstract
A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.
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Citations
23 Claims
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1. A microprocessor system, comprising:
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a register unit, said register unit comprising at least one storage location containing a value to be interpreted as a memory address;
a memory interface unit coupled to said register unit;
a memory bus coupled to said memory interface unit; and
a system memory coupled to said memory interface unit by said memory bus, said memory interface unit comprising transfer logic to increment said memory address and to generate a boundary detected signal when, after a memory bus transaction to said system memory using said memory address, said memory address after incrementing has a value that is an even multiple of 2n, where n is a nonnegative integer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of avoiding overflow and underflow of a memory boundary in a microprocessor memory page, comprising:
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accessing a boundary area of said memory page;
initiating a boundary detected signal upon said accessing; and
moving a stack pointer to a middle region of said memory page. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification