LIMITER AND SEMICONDUCTOR DEVICE USING THE SAME

• US 20070272759A1
• Filed: 04/06/2005
• Published: 11/29/2007
• Est. Priority Date: 04/09/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Granted Patent: US 7,714,633 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07735 the record carrier comprising means for protecting against electrostatic discharge
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The limiter of the invention uses as a diode a stacked gate thin film transistor (TFT) including a floating gate. When the TFT including a floating gate is used, the threshold voltage may be corrected by controlling the amount of charge accumulated in the floating gate even in the case where there are variations in the threshold voltages Vth of the TFT.

Claims

1. A limiter comprising:

a transistor including a floating gate and a control gate,

wherein the floating gate and the control gate of the transistor overlap each other with an insulating film interposed therebetween;

a drain of the transistor is connected to the control gate; and

the drain and the control gate are connected to an input terminal and an output terminal.

7. The limiter according to any one of claims 1 to 6 further comprising a connecting terminal for controlling the amount of charge accumulated in the floating gate.

8. The limiter according to any one of claims 1 to 6 further comprising a resistor.

9. The limiter according to any one of claims 1 to 6, wherein the transistor is a thin film transistor.

2. A limiter comprising:

a transistor including a floating gate and a control gate,

wherein the floating gate and the control gate of the transistor overlap each other with an insulating film interposed therebetween;

a drain of the transistor is connected to the control gate; and

a source of the transistor is connected to an input terminal and an output terminal.

3. A limiter comprising:

a plurality of transistors each includes a floating gate and a control gate,

wherein the floating gate and the control gate of each of the transistors overlap each other with an insulating film interposed therebetween;

a drain of each of the transistors is connected to the control gate;

the plurality of transistors are connected in series so as to have the same forward current direction; and

the drain and the control gate of one of the transistors, which is connected at the end, are connected to an input terminal and an output terminal.

4. A limiter comprising:

a plurality of transistors each includes a floating gate and a control gate,

wherein the floating gate and the control gate of each of the transistors overlap each other with an insulating film interposed therebetween;

a drain of each of the transistors is connected to the control gate;

the plurality of transistors are connected in series so as to have the same forward current direction; and

a source of one of the transistors, which is connected at the end, is connected to an input terminal and an output terminal.

5. A limiter comprising:

a first transistor, and

a second transistor,

wherein a floating gate and a control gate of the first transistor overlap each other with an insulating film interposed therebetween;

a drain of the first transistor is connected to the control gate of the first transistor;

a drain of the second transistor is connected to a gate of the second transistor;

the first transistor and the second transistor are connected in series so as to have the same forward current direction; and

the drain of the second transistor and the control gate are connected to an input terminal and an output terminal.

6. A limiter comprising:

a first transistor, and

a second transistor,

wherein a floating gate and a control gate of the first transistor overlap each other with an insulating film interposed therebetween;

a drain of the first transistor is connected to the control gate of the first transistor;

a drain of the second transistor is connected to a gate of the second transistor;

the first transistor and the second transistor are connected in series so as to have the same forward current direction; and

a source of the second transistor is connected to an input terminal and an output terminal.

10. A semiconductor device comprising:

an integrated circuit, and

an antenna connected to the integrated circuit,

wherein the integrated circuit includes a limiter;

the limiter includes a transistor;

a floating gate and a control gate of the transistor overlap each other with an insulating film interposed therebetween;

a drain of the transistor is connected to the control gate.

12. The semiconductor device according to claim 10 or 11, wherein the transistor is a thin film transistor.

13. The semiconductor device according to claim 10 or 11 further comprising a resistor.

11. A semiconductor device comprising an integrated circuit and an antenna connected to the integrated circuit,

wherein the integrated circuit includes a limiter, a pulse generation circuit for controlling a limit voltage of the limiter, and a booster circuit for supplying a power supply voltage to the pulse generation circuit;

the limiter includes a transistor;

a floating gate and a control gate of the transistor overlap each other with an insulating film interposed therebetween;

a drain of the transistor is connected to the control gate; and

the drain and the control gate are connected to one terminal of the resistor.