Gallium nitride material devices and associated methods

• US 20070272957A1
• Filed: 11/30/2006
• Published: 11/29/2007
• Est. Priority Date: 12/02/2005
• Status: Active Grant

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: Nitronex Corporation
• Inventors: Singhal, Sameer, Johnson, Jerry, Hanson, Allen, Therrien, Robert
• Granted Patent: US 9,608,102 B2
• Time in Patent Office: Days
• US Class Current: 257/289
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others.

Claims

1. A transistor comprising:

a gallium nitride material region;

a source electrode formed, at least in part, over the gallium nitride material region;

a gate electrode formed, at least in part, over the gallium nitride material region;

a drain electrode formed, at least in part, over the gallium nitride material region; and

a source field plate comprising a conductive material and being electrically connected to the source electrode.

2. The transistor of claim 1, wherein the source field plate extends in a direction toward the gate electrode.

3. The transistor of claim 1, wherein the source field plate extends over the gate electrode.

4. The transistor of claim 3, wherein the source field plate extends to a point between about 25% and 75% the distance between the gate electrode and the drain electrode.

5. The transistor of claim 4, wherein the source field plate extends to a point between about 40% and 60% the distance between the gate electrode and the drain electrode.

6. The transistor of claim 1, wherein the transistor is an RF transistor.

7. The transistor of claim 1, wherein the source field plate is connected to a ground potential.

8. The transistor of claim 1, wherein the source field plate is electrically connected to a contact at a backside of the transistor.

9. The transistor of claim 1, wherein the source field plate is electrically connected to a contact at a backside of the transistor using conductive material formed in a via that extends to the backside

10. The transistor of claim 1, further comprising a substrate, wherein the gallium nitride material region is formed over the substrate.

11. The transistor of claim 1, wherein the substrate is silicon.

12. The transistor of claim 1, further comprising a dielectric layer, wherein the source field plate is formed on the dielectric layer.

13. The transistor of claim 1, further comprising an encapsulation layer comprising a dielectric material, wherein the source field plate is formed on the encapsulation layer.

14. The transistor of claim 1, further comprising a passivating layer formed on the gallium nitride material region.

15. The transistor of claim 1, wherein the passivating layer defines, in part, a via in which the gate electrode is formed.

16. The transistor of claim 1, wherein a cross-sectional area at a top of the via is greater than a cross-sectional area at a bottom of the via.

17. The transistor of claim 1, wherein the gate electrode extends over a portion of the top surface of the passivating layer a distance in a direction of the drain electrode greater than a distance in a direction of the source electrode.

18. The transistor of claim 17, wherein the gate electrode extends over a portion of the top surface of the passivating layer a distance, in a direction of the source electrode, of less than 50% the distance the gate electrode extends over the passivating layer in the direction of the drain electrode.

19. The transistor of claim 1, further comprising a compositionally-graded transition layer formed between the substrate and the gallium nitride material region.

20. The transistor of claim 1, wherein the transistor is capable of operating at an output power of at least 5 W/mm.

21. The transistor of claim 1, wherein the transistor is capable of operating at an output power of at least 10 W/mm.

22. The transistor of claim 1, wherein the transistor is capable of operating at a drain efficiency of at least 70%.

23. The transistor of claim 1, wherein the transistor is capable of operating at a drain efficiency of at least 50%.

24. A method comprising:

forming a gallium nitride material region;

forming a source electrode, at least in part, over the gallium nitride material region;

forming a gate electrode, at least in part, over the gallium nitride material region;

forming a drain electrode, at least in part, over the gallium nitride material region; and

forming a source field plate comprising a conductive material that is electrically connected to the source electrode.

25. The method of claim 24, wherein the source field plate, in part, increases a power density of the transistor to at least 5 W/mm.

26. The method of claim 24, wherein the source field plate, in part, increases a power density of the transistor to at least 7 W/mm.

27. The method of claim 24, wherein the source field plate, in part, increases a power density of the transistor to at least 10 W/mm.

28. The method of claim 24, wherein the source field plate, in part, increases the efficiency to at least 50%.

29. The method of claim 24, wherein the source field plate, in part, increases the efficiency to at least 70%.

30. A method of operating a transistor comprising:

operating a transistor comprising gallium nitride material at a power density of at least 10 W/mm and a drain efficiency of at least 70%.

31. A method of operating a transistor comprising:

operating a transistor comprising gallium nitride material at a drain voltage of 28 V for a period of at least 1000 hours, while maintaining an output power that varies by less than 1 dB.

32. A method of operating a transistor comprising:

operating an RF transistor comprising a gallium nitride material formed over a silicon substrate with a gate-drain capacitance of less than 0.1 pF per mm of gate periphery.

33. The method of claim 32, wherein the transistor is an RF transistor.

34. The method of claim 32, comprising operating the transistor with a gate-drain capacitance of less than 0.1 pF per mm of gate periphery.

35. The method of claim 32, wherein the capacitance is measured at a drain-source voltage of about 28 volts.