SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME

• US 20070273018A1
• Filed: 02/26/2007
• Published: 11/29/2007
• Est. Priority Date: 03/29/2006
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Funaki, Hideyuki, Itaya, Kazuhiko, Yamada, Hiroshi, Onozuka, Yutaka
• Application Number:
  US11/678,996
• Publication Number:
  US 20070273018A1
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01041 Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

It is made possible to provide a highly integrated, thin apparatus can be obtained, even if the apparatus contains MEMS devices and semiconductor devices. A semiconductor apparatus includes: a first chip comprising a MEMS device formed therein; a second chip comprising a semiconductor device formed therein; and an adhesive layer bonding a side face of the first chip to a side face of the second chip, and having a lower Young'"'"'s modulus than the material of the first and second chips.

Claims

1. A semiconductor apparatus comprising

a first chip comprising a MEMS device formed therein;

a second chip comprising a semiconductor device formed therein; and

an adhesive layer bonding a side face of the first chip to a side face of the second chip, and having a lower Young'"'"'s modulus than the material of the first and second chips.

2. The apparatus according to claim 1, wherein a principal face of the first chip and a principal face of the second chip are located substantially in the same plane.

3. The apparatus according to claim 2, further comprising:

another adhesive layer formed on a bottom face of the first chip, a bottom face of the second chip, and a face of the adhesive layer on the side of the bottom faces of the first and second chips.

4. The apparatus according to claim 2, further comprising:

an insulating layer provided so as to cover the principal face of the first chip, the principal face of the second chip, and a face of the adhesive layer on the side of the principal faces of the first and second chips; and

a wire provided on the insulating layer and electrically connects the MEMS device and the semiconductor device.

5. The apparatus according to claim 4, wherein a width of the wire on the adhesive layer is greater than a width of the wire on the first and second chips.

6. The apparatus according to claim 1, wherein a bottom face of the first chip and a principal face of the second chip are located substantially in the same plane.

7. The apparatus according to claim 6, further comprising:

a wire electrically connecting the MEMS device and the semiconductor device, and configured to penetrate the adhesive layer from one face to the other thereof.

8. The apparatus according to claim 1, wherein the first chip and the second chip have substantially the same height.

9. The apparatus according to claim 1, wherein the adhesive layer that bonds the side face of the first chip to the side face of the second chip is made of epoxy resin.

10. The apparatus according to claim 1, wherein the adhesive layer that bonds the side face of the first chip to the side face of the second chip has a Young'"'"'s modulus of 10 GPa or less.

11. A semiconductor apparatus comprising:

a first chip comprising a MEMS device formed therein;

a second chip comprising a semiconductor device formed therein;

a first adhesive layer bonding a side face of the first chip to a side face of the second chip, and having a lower Young'"'"'s modulus than the material of the first and second chips;

a third chip comprising a MEMS device formed therein; and

a fourth chip comprising a semiconductor device formed therein; and

a second adhesive layer bonding a side face of the third chip to a side face of the fourth chip, and having a lower Young'"'"'s modulus than the material of the third and fourth chips.

12. The apparatus according to claim 11, wherein:

a principal face of the first chip and a principal face of the second chip are located substantially in the same plane; and

a principal face of the third chip and a principal face of the fourth chip are located substantially in the same plane.

13. The apparatus according to claim 11, wherein:

a bottom face of the first chip and a principal face of the second chip are located substantially in the same plane; and

a bottom face of the third chip and a principal face of the fourth chip are located substantially in the same plane.

14. The apparatus according to claim 11, wherein the first and second adhesive layers are made of epoxy resin.

15. The apparatus according to claim 11, wherein the first and second adhesive layer each have a Young'"'"'s modulus of 10 GPa or less.

16. A method for manufacturing a semiconductor apparatus, comprising:

forming a plurality of semiconductor devices on a first semiconductor substrate;

forming a first protection film that covers the plurality of semiconductor devices;

temporarily bonding the first protection film to a first temporary adhesive layer that is formed on a surface of a first substrate that is independent of the first semiconductor substrate;

forming a plurality of semiconductor chips by cutting the first semiconductor substrate and dividing the plurality of semiconductor devices;

removing one of the semiconductor chips from the first temporary adhesive layer by selectively picking up the one semiconductor chip;

temporarily bonding and transferring the picked-up semiconductor chip onto a second adhesive layer that is formed on a surface of a second substrate that is independent of the first substrate;

forming a plurality of MEMS devices on a second semiconductor substrate that is independent of the first semiconductor substrate;

forming a second protection film that covers the plurality of MEMS devices;

temporarily bonding the second protection film to a third temporary adhesive layer that is formed on a surface of a third substrate that is independent of the first substrate and the second substrate;

forming a plurality of MEMS chips by cutting the second semiconductor substrate and dividing the plurality of MEMS devices;

removing one of the MEMS chips from the third temporary adhesive layer by selectively picking up the one MEMS chip;

temporarily bonding and transferring the picked-up MEMS chip onto the second temporary adhesive layer formed on the surface of the second substrate;

forming a first adhesive layer so as to cover the MEMS chip and the semiconductor chip and to fill a space between the MEMS chip and the semiconductor chip;

making the heights of the MEMS chip and the semiconductor chip equal to each other with respect to the second temporary adhesive layer by polishing the first adhesive layer and polishing at least one of the MEMS chip and the semiconductor chip; and

removing the MEMS chip and the semiconductor chip from the second temporary adhesive layer by bonding the MEMS chip and the semiconductor chip to a second adhesive layer that is formed on a supporting substrate.