Interconnect structure and formation for package stacking of molded plastic area array package

• US 20070273049A1
• Filed: 01/11/2007
• Published: 11/29/2007
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Zhao, Sam Ziqun, Khan, Rezaur Rahman
• Granted Patent: US 7,714,453 B2
• Time in Patent Office: Days
• US Class Current: 257/787
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Apparatuses, methods, and systems for improved integrated circuit packages are described. An integrated circuit (IC) package includes a substrate having opposing first and second surfaces, an IC die, a plurality of conductive elements, and an encapsulating material. The substrate has a plurality of contact pads on the first surface that are electrically coupled to a plurality of electrically conductive features on the second surface. The plurality of conductive elements is formed on the first surface of the substrate. The IC die is located on the first surface of the substrate. The encapsulating material encapsulates the IC die and a portion of each element of the plurality of conductive elements.

Claims

1. An integrated circuit (IC) package, comprising:

a substrate having opposing first and second surfaces;

a plurality of contact pads on the first surface of the substrate electrically connected to a plurality of electrically conductive features on the second surface of the substrate;

an integrated circuit (IC) die mounted to the first surface of the substrate;

a plurality of conductive elements formed on the plurality of contact pads on the first surface of the substrate; and

an encapsulating material, that encapsulates the IC die and the plurality of conductive elements, wherein a portion of each conductive element of the plurality of conductive elements is exposed at a surface of the encapsulating material.

2. The package of claim 1, further comprising:

an electrical component mounted to a first surface of the encapsulating material such that a plurality of electrically conductive members of the electrical component is electrically coupled to the plurality of conductive elements.

3. The package of claim 2, wherein the electrical component is at least one of a resistor, capacitor, or inductor.

4. The package of claim 2, wherein the electrical component is a ball-grid array (BGA) package, land-grid array (LGA) package, or a through-hole package.

5. The package of claim 1, wherein the surface of the encapsulating material is planar.

6. The package of claim 1, wherein the surface of the encapsulating material is non-planar.

7. The package of claim 6, wherein the surface of the encapsulating material is a shelf formed in the encapsulating material.

8. The package of claim 6, wherein the surface of the encapsulating material is a trench formed in the encapsulation material.

9. The package of claim 1, wherein a plurality of solder balls is formed on the electrically conductive features on the second surface of the substrate.

10. The package of claim 1, wherein the plurality of conductive elements is a plurality of solder balls.

11. The package of claim 1, wherein the plurality of conductive elements is a plurality of metallic posts.

12. The package of claim 1, wherein the substrate is a flex tape substrate.

13. The package of claim 1, wherein the IC die is mounted to the first surface of the substrate using an adhesive.

14. The package of claim 1, further comprising:

a wirebond that couples a bond pad on a first surface of the IC die to a bond finger on the first surface of the substrate.

15. A method for forming a stacked integrated circuit (IC) package, comprising:

mounting an IC die to a first surface of a substrate having a plurality of contact pads on the first surface that are electrically connected through the substrate to a plurality of electrically conductive features on a second surface of the substrate;

forming a plurality of conductive elements on the plurality of contact pads on the first surface of the substrate; and

encapsulating the die and at least a portion of each element of the plurality of conductive elements on the first surface of the substrate with an encapsulating material.

16. The method of claim 15, further comprising:

removing a portion of the encapsulating material to expose a portion of each conductive element of the plurality of conductive elements at a surface of the encapsulating material.

17. The method of claim 16, wherein the removing step comprises:

removing a planar layer of the encapsulating material such that a portion of each conductive element of the plurality of conductive elements at the surface of the encapsulating material is exposed.

18. The method of claim 16, wherein the removing step comprises:

removing a peripheral edge region of the encapsulating material to expose a portion of each conductive element of the plurality of conductive elements at the surface of the encapsulating material.

19. The method of claim 16, wherein the removing step comprises:

forming a trench in the encapsulating material to expose a portion of each conductive element of the plurality of conductive elements at the surface of the encapsulating material.

20. The method of claim 16, wherein the removing step comprises:

grinding the encapsulation material to remove the portion of the encapsulation material.

21. The method of claim 16, wherein the removing step comprises:

routing the encapsulation material to remove the portion of the encapsulation material.

22. The method of claim 16, wherein the removing step comprises:

etching the encapsulation material using a chemical etchant to remove the portion of the encapsulation material.

23. The method of claim 15 further comprising:

forming a plurality of solder balls on the plurality of conductive features on the second surface of the substrate.

24. The method of claim 15, wherein the encapsulation step comprises:

encapsulating the die and first plurality of conductive elements using a dam-and-fill process, a mold cap injection molding process, or a strip or panel over-molding process.

25. The method of claim 15, further comprising:

mounting an electrical component to a first surface of the encapsulating material such that a plurality electrically conductive members of the electrical component is electrically coupled to the plurality of conductive elements.

26. The method of claim 25, wherein the electrical component is a circuit element, wherein the mounting of the electrical component step comprises:

mounting the circuit element to the first surface of the encapsulating material such that at least one lead of the circuit element is electrically coupled to the plurality of conductive elements.

27. The method of claim 25, wherein the electrical component is a land-grid array package (LGA), wherein the mounting of the electrical component step comprises:

mounting the LGA package to the first surface of the encapsulating material such that a plurality of contact pads of the LGA package is electrically coupled to the plurality of conductive elements by applying a solder paste to the plurality of ball pads of the LGA.

28. The method of claim 25, wherein the electrical component is a through-hole package, wherein the mounting of the electrical component step comprises:

mounting the through-hole package to the first surface of the encapsulating material such that a plurality of terminals of the through hole package is electrically coupled to the plurality of conductive elements.

29. The method of claim 15, further comprising:

coupling a plurality of bond pads on a first surface of the IC die to a plurality of bond fingers on the first surface of the substrate.