Millimeter-wave cascode amplifier gain boosting technique

• US 20070273445A1
• Filed: 05/09/2007
• Published: 11/29/2007
• Est. Priority Date: 05/10/2006
• Status: Active Grant

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Pinel, Stephane, Laskar, Joy, Sen, Padmanava, Sarkar, Saikat
• Granted Patent: US 7,489,201 B2
• Time in Patent Office: Days
• US Class Current: 330/278
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 2200/181 A coil being added in the gate circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/60 Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators H03F3/54 takes precedence

Abstract

Disclosed is a gain boosting technique for use with millimeter-wave cascode amplifiers. The exemplary technique may be implemented using a 0.18 μm SiGe process (F_T=140 GHz). It has also been shown that the technique is effective for CMOS processes with comparable F_T. An exemplary gain-enhanced cascode stage was measured to have higher than 9 dB gain with a 1-dB bandwidth above 6 GHz with a DC power consumption of 13 mW. In addition, one cascode stage without gain boosting may be cascaded with two gain-boosted cascode amplifier stages to implement a three-stage LNA. The measured stable gain is higher than 24 dB at 60 GHz with a 3-dB bandwidth of 3.1 GHz for 25 mW of DC power consumption. It is believed that this is the first 60 GHz LNA with a higher than 20 dB gain using a 0.18 μm SiGe process.

Claims

1. Cascode core apparatus comprising:

a common emitter transistor;

a common base transistor cascaded with the common emitter transistor; and

an inductance coupled between a base of the common base transistor and a capacitively coupled RF ground, which inductance increases the maximum available gain of the apparatus.

2. The apparatus recited in claim 1 which further comprises:

an output matching network having an RF output coupled between a voltage source and the common base transistor;

an input matching network having an RF input that is coupled to a base of the common emitter transistor; and

a DC bias network coupled to the input matching network.

7. The apparatus recited in claim 1 further comprising:

an output matching network having an RF output coupled to a collector of the common base transistor;

an input matching network having an RF input that is coupled to a base of the common emitter transistor; and

a DC bias network for providing bias for the common base and common emitter transistors;

which apparatus comprises a one-stage gain-boosted cascode amplifier stage.

8. The apparatus recited in claim 7 which is configured to operate at a frequency range between 57 and 64 GHz.

9. The apparatus recited in claim 7 further comprising:

an unboosted one-stage cascode amplifier stage coupled to an input of the gain-boosted cascode amplifier stage; and

a second one-stage gain-boosted cascode amplifier stage coupled to an output of the one-stage gain-boosted cascode amplifier stage.

10. The apparatus recited in claim 9 which is configured to operate at a frequency range between 57 and 64 GHz.

16. The method recited in claim 10 wherein fabricating the cascode amplifier is achieved using a 0.13 μ

m CMOS process.

3. The apparatus recited in claim 3 wherein the inductance comprises a microstrip inductance.

4. The apparatus recited in claim 3 wherein the inductance comprises a lumped inductance.

5. The apparatus recited in claim 3 wherein the inductance comprises a coplanar waveguide inductance.

6. The apparatus recited in claim 3 wherein the inductance comprises a microstrip inductance.

11. A method for providing gain boosting in a cascode amplifier, comprising

fabricating a cascode amplifier comprising a common emitter transistor, a common base transistor cascaded with the common emitter transistor, an output matching network having an RF output coupled to a collector of the common base transistor, an input matching network having an RF input that is coupled to a base of the common emitter transistor, and a DC bias network for providing bias for the common base and common emitter transistors;

and

coupling an inductance between a base of the common base transistor and a capacitively coupled RF ground, so as to increase the gain of the cascode amplifier.

12. The method recited in claim 11 wherein the gain boosting of the cascode amplifier is achieved without increasing the area of the amplifier and without increasing the DC power consumption.

13. The method recited in claim 11 wherein fabricating the cascode amplifier is achieved using a SiGe process

14. The method recited in claim 11 wherein fabricating the cascode amplifier is achieved using a 0.18 μ

m SiGe process

15. The method recited in claim 11 wherein fabricating the cascode amplifier is achieved using a CMOS process.

17. The method recited in claim 11 wherein the cascode amplifier comprises a one-stage gain-boosted cascode amplifier stage, and wherein the method further comprises:

fabricating a second cascode amplifier comprising a common emitter transistor, a common base transistor cascaded with the common emitter transistor, an output matching network having an RF output coupled to a collector of the common base transistor, an input matching network having an RF input that is coupled to a base of the common emitter transistor, and a DC bias network for providing bias for the common base and common emitter transistors, which second cascode amplifier comprises an unboosted one-stage cascode amplifier stage;

coupling the unboosted one-stage cascode amplifier stage to an input of the gain-boosted cascode amplifier stage;

fabricating a third cascode amplifier comprising a common emitter transistor, a common base transistor cascaded with the common emitter transistor, an output matching network having an RF output coupled to a collector of the common base transistor, an input matching network having an RF input that is coupled to a base of the common emitter transistor, and a DC bias network for providing bias for the common base and common emitter transistors;

coupling an inductance between a base of the common base transistor and a capacitively coupled RF ground of the third cascode amplifier so as to form a second gain boosted cascode amplifier; and

coupling the second gain boosted cascode amplifier to an output of the gain-boosted cascode amplifier.

18. The method recited in claim 17 wherein fabricating is achieved using a SiGe process

19. The method recited in claim 17 wherein fabricating is achieved using a CMOS process.

20. The method recited in claim 17 wherein fabrication produces an amplifier structure that operates at a frequency range between 57 and 64 GHz.