HIGH RESOLUTION TIME-TO-DIGITAL CONVERTER AND METHOD THEREOF

• US 20070273569A1
• Filed: 05/26/2006
• Published: 11/29/2007
• Est. Priority Date: 05/26/2006
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Lin, Chia-Liang
• Granted Patent: US 7,629,915 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60

Abstract

A time-to-digital converter (TDC) is disclosed, the TDC comprising: a plurality of parallel circuits for receiving a common first clock and for generating a plurality of delayed clocks; a plurality of sampling circuits for receiving and sampling said delayed clocks at an edge of a second clock to generate a plurality of decisions, respectively; and a decoder for receiving said decisions and for generating a digital output accordingly.

Claims

1. A time-to-digital converter comprising:

a plurality of parallel circuits for receiving a common first clock and for generating a plurality of delayed clocks, wherein the delayed clocks have different timings;

a plurality of sampling circuits for sampling said delayed clocks according to a second clock to generate a plurality of decisions, respectively; and

a decoder for receiving said decisions and for generating a digital output accordingly.

2. The converter of claim 1, wherein said delayed clocks have varying amounts of delay.

3. The converter of claim 2, wherein the timings of said delayed clocks form a sequence approximating an arithmetic sequence.

4. The converter of claim 3, wherein the decoder is a thermometer code decoder.

5. The converter of claim 3, wherein the digital output is a sum of said decisions.

6. The converter of claim 3, wherein the digital output is a sum of said decisions plus a fixed offset.

7. A method of time-to-digital conversion, the method comprising:

receiving a common first clock and generating accordingly a plurality of delayed clocks using a plurality of parallel circuits;

generating a plurality of decisions by sampling said delayed clocks at an edge of a second clock; and

decoding said decisions into a digital output.

8. The method of claim 7, wherein said delayed clocks have varying amounts of delay.

9. The method of claim 8, wherein the timings of said delayed clocks form a sequence approximating an arithmetic sequence.

10. The method of claim 9, wherein the decoding further comprises using a thermometer decoder.

11. The method of claim 9, wherein the decoding further comprises summing said decisions.

12. The method of claim 9, wherein the decoding further comprising summing said decisions and a fixed offset.

13. A method of time-to-digital conversion, the method comprising:

receiving a common first clock;

generating a first group of delayed clocks from the common first clock using a plurality of parallel circuits;

generating a first group of decisions by sampling the first group of delayed clocks according to a second clock;

decoding the first group of decisions into a first timing estimate signal;

generating a second group of delayed clocks from the common first clock, wherein the delay time of the second group of delayed clocks and that of the first group of delayed clocks are different;

generating a second group of decisions by sampling the second group of delayed clocks at an edge of a third clock;

decoding the second group of decisions into a second timing estimate signal; and

generating a final timing estimate signal according to the first timing estimate signal and the second timing estimate signal.

14. The method of claim 13, wherein the timings of the first delay group of delayed clocks form a sequence approximating an arithmetic sequence.

15. The method of claim 14, wherein the decoding of the first group of decisions further comprises using a first thermometer code decoder.

16. The method of claim 13, wherein the timings of the second delay group of delayed clocks form a sequence approximating an arithmetic sequence.

17. The method of claim of 16, wherein the decoding of the second group of decisions further comprises using a second thermometer-code decoder.

18. The method of claim 13, wherein the selecting further comprises:

detecting a saturation condition for the first timing estimate.

19. The method of claim 18, wherein the selecting further comprises:

choosing the first timing estimate signal as the final timing estimate signal unless the saturation condition is detected.

20. The method of claim 13, wherein the selecting further comprises:

detecting a zero condition for the second timing estimate.

21. The method of claim 20, wherein the selecting further comprises:

choosing the second timing estimate as the final timing estimate signal unless the zero condition is detected.

22. A digital clock generator comprising:

a time-to-digital converter (TDC) module comprising a first TDC comprising;

a plurality of parallel circuits for generating a first group of delayed clocks according to a first clock;

a first group of sampling circuits to generate a first group of decisions according to a second clock and the first group of delayed clocks, and

a first circuit for generating a first tentative timing estimate signal according to the first group of decisions;

a loop filter for receiving the first timing estimate signal and for generating a frequency control signal; and

a DCO (digitally controlled oscillator) for receiving the frequency control signal and for generating an output clock.

23. The clock generator of claim 22, wherein said parallel circuits have varying amounts of delay and the amounts of delay form a sequence approximating an arithmetic sequence.

24. The clock generator of claim 22, wherein:

the first group of delayed clocks are obtained by delaying the first clock using said parallel circuits; and

the first group of decisions are obtained by sampling the first group of the delayed clocks at an edge of a third clock derived from the second clock.

25. The clock generator of claim 22, wherein:

the first group of delayed clocks are obtained by delaying the second clock using said parallel circuits; and

the first group of decisions are obtained by sampling the first group of the delayed clocks at an edge of a third clock derived from the first clock.

26. The clock generator of claim 22, wherein the TDC module further comprises:

a second TDC for receiving the first clock and the second clock and for generating a second timing estimate signal indicative of a timing difference between the first clock and the second clock.

27. The clock generator of claim 26, wherein the TDC further comprises a multiplexing circuit to select one of the first tentative timing estimate signal and the second tentative timing estimate signal as the timing estimate signal.

28. The PLL of claim 27, wherein the first tentative timing estimate signal is selected unless the first tentative timing estimate is saturated.

29. The PLL of claim 27, wherein the second tentative timing estimate signal is selected unless the second tentative timing estimate is nearly zero.

30. A method of performing timing detection, the method comprises:

using a plurality of parallel circuits to generate a plurality of derived clocks from a common first clock;

determining a plurality of relative timing relationships between said derived clocks and a second clock; and

determining a timing difference between the first clock and the second clock based on said relative timing relationships.

31. The method of claim 30, wherein said derived clocks have different timings.

32. The method of claim 30, wherein the timings of said derived clocks form a sequence approximating an arithmetic sequence.

33. The method of claim 30, wherein the relative timing relationships are obtained by sampling the derived clocks using the second clock.

34. The method of claim 30, wherein the determining comprises using a decoder to convert said relative timing relationships into the timing difference.

35. The method of claim 30, wherein the resolution of the timing detection is less than 20 ps.

36. A method of time-to-digital conversion, the method comprising:

receiving a first clock and generating accordingly a first group of delayed clocks using a first group of parallel circuits;

generating a first group of decisions by sampling the first group of delayed clocks according to a second clock;

decoding the first group of decisions into a first tentative timing estimate;

receiving the second clock and generating accordingly a second group of delayed clocks using a second group of parallel circuits;

generating a second group of decisions by sampling the second group of delayed clocks according to the first clock; and

decoding the second group of decisions into a second tentative timing estimate; and

generating a final timing estimate according to the first tentative timing estimate and the second timing estimate.

37. The method of claim 36, wherein the timings of the first group of delay clocks form a first sequence approximating an arithmetic sequence.

38. The method of claim 37, wherein the first tentative timing estimate is a sum of the first group of decisions.

39. The method of claim 36, wherein the timings of the second group of delay clocks form a second sequence approximating an arithmetic sequence.

40. The method of claim 39, wherein the second tentative timing estimate is a sum of the second group of decisions.

41. The method of claim 36, wherein the final timing estimate is a difference between the first tentative timing estimate and the second tentative timing estimate.