HYBRID INTEGRATION BASED ON WAFER-BONDING OF DEVICES TO AISb MONOLITHICALLY GROWN ON Si

• US 20070275492A1
• Filed: 01/11/2007
• Published: 11/29/2007
• Est. Priority Date: 01/11/2006
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Balakrishnan, Ganesh, Huffaker, Diana, Dawson, Larry
• Granted Patent: US 7,700,395 B2
• Time in Patent Office: Days
• US Class Current: 438/46
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01S 5/0215 Bonding to the substrate
• CPC Class Codes: H01S 5/028 Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
• CPC Class Codes: H01S 5/183 having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

Abstract

Exemplary embodiments provide a semiconductor fabrication method including a combination of monolithic integration techniques with wafer bonding techniques. The resulting semiconductor devices can be used in a wide variety of opto-electronic and/or electronic applications such as lasers, light emitting diodes (LEDs), phototvoltaics, photodetectors and transistors. In an exemplary embodiment, the semiconductor device can be formed by first forming an active-device structure including an active-device section disposed on a thinned III-V substrate. The active-device section can include OP and/or EP VCSEL devices. A high-quality monolithic integration structure can then be formed with low defect density through an interfacial misfit dislocation. In the high-quality monolithic integration structure, a thinned III-V mating layer can be formed over a silicon substrate. The thinned III-V substrate of the active-device structure can subsequently be wafer-bonded onto the thinned III-V mating layer of the high-quality monolithic integration structure forming an optoelectronic semiconductor device on silicon.

Claims

1. A method for forming a semiconductor device comprising:

forming an active-device structure comprising an active-device section formed on a III-V substrate;

thinning the III-V substrate of the active-device structure;

forming a high-quality monolithic integration structure through an interfacial misfit dislocation, wherein the high-quality monolithic integration structure comprises a thinned III-V mating layer formed on a III-V nucleation layer formed on a silicon substrate; and

wafer-bonding the thinned III-V substrate of the active-device structure onto the thinned III-V mating layer of the high-quality monolithic integration structure.

2. The method of claim 1, wherein the active-device section comprises one or more devices selected from the group consisting of lasers, LEDs, phototvoltaics, detectors and transistors.

3. The method of claim 1, wherein the active-device section comprises one or more of an optically-pumped VCSEL and an electrically-pumped VCSEL.

4. The method of claim 1, wherein the active-device section comprises a multiple quantum well (MQW) active region, wherein the MQW active region comprises a material selected from the group consisting of GaSb, AlGaSb, InSb, InGaSb, and InAlSb.

5. The method of claim 1, wherein one or more of the thinned III-V substrate of the active-device structure and the thinned III-V mating layer of the high-quality monolithic integration structure comprise a material selected from the group consisting of GaSb, InSb, GaAs, InP, InAs, AlAs, AlGaAs, InGaSb, and GaN.

6. The method of claim 1, wherein the high-quality monolithic integration structure has a defect density of about 10⁶ cm⁻

2 or less and a strain relief of about 98% or higher.

7. The method of claim 1, wherein the thinned III-V mating layer of the high-quality monolithic integration structure has a thickness of about 100 Å

or less.

8. The method of claim 1, wherein the interfacial misfit dislocation comprises a 2-dimensional array that is laterally propagated at the interface between the III-V nucleation layer and the silicon substrate of the high-quality monolithic integration structure.

9. The method of claim 1, wherein the III-V nucleation layer of the high-quality monolithic integration structure comprises an AlSb layer.

10. A method for forming a semiconductor device comprising:

forming an active-device structure, wherein the active-device structure comprises a first thinned III-V mating layer formed on an active-device section formed on a supporting substrate;

forming a high-quality monolithic integration structure through an interfacial misfit dislocation, wherein the high-quality monolithic integration structure comprises a second thinned III-V mating layer formed on a III-V nucleation layer formed on a silicon substrate;

wafer-bonding the first thinned III-V mating layer of the active-device structure onto the second thinned III-V mating layer of the high-quality monolithic integration structure; and

exposing the active-device section by removing the supporting substrate.

11. The method of claim 10, further comprising an etch-stop layer formed between the active-device section and the supporting substrate of the active-device structure.

12. The method of claim 10, further comprising flipping the active-device structure upside down prior to wafer-bonding the first thinned III-V mating layer of the active-device structure onto the second thinned III-V mating layer of the high-quality monolithic integration structure.

13. The method of claim 10, wherein one or more of the first and the second thinned III-V mating layer comprise a material selected from the group consisting of GaSb, InSb, GaAs, InP, InAs, AlAs, AlGaAs, InGaSb, and GaN.

14. The method of claim 10, wherein the second thinned III-V mating layer of the high-quality monolithic integration structure has a thickness of about 100 Å

or less.

15. The method of claim 10, wherein the interfacial misfit dislocation comprises a 2-dimensional array that is laterally propagated at the interface between the III-V nucleation layer and the silicon substrate of the high-quality monolithic integration structure.

16. The method of claim 10, wherein the III-V nucleation layer of the high-quality monolithic integration structure comprises an AlSb layer.

17. The method of claim 10, wherein the active-device section comprises a multiple quantum well (MQW) active region, wherein the MQW active region comprises a material selected from the group consisting of GaSb, AlGaSb, InSb, InGaSb, and InAlSb.

18. The method of claim 10, wherein the active-device section comprises one or more of an optically-pumped VCSEL and an electrically-pumped VCSEL.

19. The method of claim 10, wherein the active-device section comprises one or more devices selected from the group consisting of lasers, LEDs, phototvoltaics, detectors and transistors.

20. A method for forming a semiconductor device comprising:

epitaxially forming a VCSEL device on a GaSb substrate, wherein the VCSEL device is an optically-pumped VCSEL or an electrically-pumped VCSEL;

thinning the GaSb substrate of the VCSEL device;

monolithically forming a thinned GaSb mating layer on an AlSb nucleation layer formed on a silicon substrate through an interfacial misfit dislocation for a low defect density, wherein the thinned GaSb mating layer has a thickness of about 100 Å

or less; and

wafer-bonding the thinned GaSb substrate of the VCSEL device onto the thinned GaSb mating layer formed on the AlSb nucleation layer on the silicon substrate.